![Philipp Zabel](/assets/img/avatar_default.png)
Commit a53e35db70
("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.
No functional changes.
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Joachim Eastwood <manabian@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
289 lines
7.2 KiB
C
289 lines
7.2 KiB
C
/*
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* NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver
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*
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* Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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/* Registers */
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#define LPC18XX_EEPROM_AUTOPROG 0x00c
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#define LPC18XX_EEPROM_AUTOPROG_WORD 0x1
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#define LPC18XX_EEPROM_CLKDIV 0x014
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#define LPC18XX_EEPROM_PWRDWN 0x018
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#define LPC18XX_EEPROM_PWRDWN_NO 0x0
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#define LPC18XX_EEPROM_PWRDWN_YES 0x1
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#define LPC18XX_EEPROM_INTSTAT 0xfe0
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#define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2)
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#define LPC18XX_EEPROM_INTSTATCLR 0xfe8
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#define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2)
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/* Fixed page size (bytes) */
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#define LPC18XX_EEPROM_PAGE_SIZE 0x80
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/* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
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#define LPC18XX_EEPROM_CLOCK_HZ 1500000
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/* EEPROM requires 3 ms of erase/program time between each writing */
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#define LPC18XX_EEPROM_PROGRAM_TIME 3
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struct lpc18xx_eeprom_dev {
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struct clk *clk;
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void __iomem *reg_base;
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void __iomem *mem_base;
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struct nvmem_device *nvmem;
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unsigned reg_bytes;
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unsigned val_bytes;
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int size;
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};
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static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom,
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u32 reg, u32 val)
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{
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writel(val, eeprom->reg_base + reg);
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}
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static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom,
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u32 reg)
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{
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return readl(eeprom->reg_base + reg);
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}
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static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom)
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{
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unsigned long end;
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u32 val;
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/* Wait until EEPROM program operation has finished */
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end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10);
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while (time_is_after_jiffies(end)) {
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val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT);
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if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) {
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR,
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LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST);
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return 0;
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}
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usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC,
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(LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC);
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}
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return -ETIMEDOUT;
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}
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static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg,
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void *val, size_t bytes)
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{
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struct lpc18xx_eeprom_dev *eeprom = context;
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unsigned int offset = reg;
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int ret;
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/*
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* The last page contains the EEPROM initialization data and is not
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* writable.
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*/
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if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) ||
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(reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE))
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return -EINVAL;
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_NO);
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/* Wait 100 us while the EEPROM wakes up */
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usleep_range(100, 200);
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while (bytes) {
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writel(*(u32 *)val, eeprom->mem_base + offset);
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ret = lpc18xx_eeprom_busywait_until_prog(eeprom);
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if (ret < 0)
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return ret;
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bytes -= eeprom->val_bytes;
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val += eeprom->val_bytes;
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offset += eeprom->val_bytes;
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}
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_YES);
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return 0;
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}
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static int lpc18xx_eeprom_read(void *context, unsigned int offset,
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void *val, size_t bytes)
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{
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struct lpc18xx_eeprom_dev *eeprom = context;
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_NO);
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/* Wait 100 us while the EEPROM wakes up */
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usleep_range(100, 200);
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while (bytes) {
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*(u32 *)val = readl(eeprom->mem_base + offset);
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bytes -= eeprom->val_bytes;
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val += eeprom->val_bytes;
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offset += eeprom->val_bytes;
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}
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_YES);
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return 0;
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}
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static struct nvmem_config lpc18xx_nvmem_config = {
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.name = "lpc18xx-eeprom",
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.stride = 4,
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.word_size = 4,
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.reg_read = lpc18xx_eeprom_read,
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.reg_write = lpc18xx_eeprom_gather_write,
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.owner = THIS_MODULE,
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};
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static int lpc18xx_eeprom_probe(struct platform_device *pdev)
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{
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struct lpc18xx_eeprom_dev *eeprom;
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struct device *dev = &pdev->dev;
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struct reset_control *rst;
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unsigned long clk_rate;
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struct resource *res;
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int ret;
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eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL);
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if (!eeprom)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
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eeprom->reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(eeprom->reg_base))
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return PTR_ERR(eeprom->reg_base);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
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eeprom->mem_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(eeprom->mem_base))
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return PTR_ERR(eeprom->mem_base);
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eeprom->clk = devm_clk_get(&pdev->dev, "eeprom");
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if (IS_ERR(eeprom->clk)) {
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dev_err(&pdev->dev, "failed to get eeprom clock\n");
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return PTR_ERR(eeprom->clk);
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}
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ret = clk_prepare_enable(eeprom->clk);
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if (ret < 0) {
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dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret);
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return ret;
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}
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rst = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(rst)) {
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dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst));
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ret = PTR_ERR(rst);
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goto err_clk;
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}
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ret = reset_control_assert(rst);
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if (ret < 0) {
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dev_err(dev, "failed to assert reset: %d\n", ret);
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goto err_clk;
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}
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eeprom->val_bytes = 4;
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eeprom->reg_bytes = 4;
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/*
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* Clock rate is generated by dividing the system bus clock by the
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* division factor, contained in the divider register (minus 1 encoded).
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*/
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clk_rate = clk_get_rate(eeprom->clk);
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clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1;
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate);
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/*
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* Writing a single word to the page will start the erase/program cycle
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* automatically
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*/
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG,
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LPC18XX_EEPROM_AUTOPROG_WORD);
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_YES);
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eeprom->size = resource_size(res);
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lpc18xx_nvmem_config.size = resource_size(res);
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lpc18xx_nvmem_config.dev = dev;
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lpc18xx_nvmem_config.priv = eeprom;
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eeprom->nvmem = nvmem_register(&lpc18xx_nvmem_config);
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if (IS_ERR(eeprom->nvmem)) {
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ret = PTR_ERR(eeprom->nvmem);
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goto err_clk;
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}
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platform_set_drvdata(pdev, eeprom);
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return 0;
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err_clk:
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clk_disable_unprepare(eeprom->clk);
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return ret;
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}
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static int lpc18xx_eeprom_remove(struct platform_device *pdev)
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{
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struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev);
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int ret;
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ret = nvmem_unregister(eeprom->nvmem);
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if (ret < 0)
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return ret;
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clk_disable_unprepare(eeprom->clk);
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return 0;
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}
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static const struct of_device_id lpc18xx_eeprom_of_match[] = {
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{ .compatible = "nxp,lpc1857-eeprom" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match);
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static struct platform_driver lpc18xx_eeprom_driver = {
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.probe = lpc18xx_eeprom_probe,
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.remove = lpc18xx_eeprom_remove,
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.driver = {
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.name = "lpc18xx-eeprom",
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.of_match_table = lpc18xx_eeprom_of_match,
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},
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};
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module_platform_driver(lpc18xx_eeprom_driver);
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MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
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MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver");
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MODULE_LICENSE("GPL v2");
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