358 lines
8.6 KiB
C
358 lines
8.6 KiB
C
/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __LINUX_REGULATOR_TPS6518x_H_
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#define __LINUX_REGULATOR_TPS6518x_H_
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/*
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* EPDC PMIC I2C address
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* PAPYRUS II 1p1 and later uses 0x68, others 0x48
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*/
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#define EPDC_PMIC_I2C_ADDR 0x68
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/*
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* currently supported rev IDs
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*/
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//#define TPS65180_PASS1 0x54
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//#define TPS65181_PASS1 0x55
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#define TPS65180_PASS1 0x50
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#define TPS65181_PASS1 0x51
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#define TPS65180_PASS2 0x60
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#define TPS65181_PASS2 0x61
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#define TPS65185_PASS0 0x45
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#define TPS65186_PASS0 0x46
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#define TPS65185_PASS1 0x55
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#define TPS65186_PASS1 0x56
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#define TPS65185_PASS2 0x65
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#define TPS65186_PASS2 0x66
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/*
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* PMIC Register Addresses
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*/
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enum {
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REG_TPS6518x_TMST_VAL = 0x0,
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REG_TPS65185_ENABLE,
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REG_TPS65185_VADJ,
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REG_TPS65185_VCOM1,
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REG_TPS65185_VCOM2,
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REG_TPS65185_INT_EN1,
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REG_TPS65185_INT_EN2,
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REG_TPS65185_INT1,
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REG_TPS65185_INT2,
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REG_TPS65185_UPSEQ0,
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REG_TPS65185_UPSEQ1,
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REG_TPS65185_DWNSEQ0,
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REG_TPS65185_DWNSEQ1,
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REG_TPS65185_TMST1,
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REG_TPS65185_TMST2,
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REG_TPS6518x_PG,
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REG_TPS6518x_REVID,
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TPS6518x_REG_NUM,
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};
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enum {
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REG_TPS65180_TMST_VAL = 0x0,
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REG_TPS65180_ENABLE,
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REG_TPS65180_VP_ADJUST,
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REG_TPS65180_VN_ADJUST,
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REG_TPS65180_VCOM_ADJUST,
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REG_TPS65180_INT_EN1,
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REG_TPS65180_INT_EN2,
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REG_TPS65180_INT1,
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REG_TPS65180_INT2,
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REG_TPS65180_PWRSEQ0,
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REG_TPS65180_PWRSEQ1,
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REG_TPS65180_PWRSEQ2,
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REG_TPS65180_TMST_CONFIG,
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REG_TPS65180_TMST_OS,
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REG_TPS65180_TMST_HYST,
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REG_TPS65180_PG_STATUS,
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REG_TPS65180_REVID,
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REG_TPS65180_FIX_READ_PTR,
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TPS65180_REG_NUM,
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};
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#define TPS6518x_MAX_REGISTER 0xFF
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/*
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* Bitfield macros that use rely on bitfield width/shift information.
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*/
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#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH))
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#define BITFVAL(field, val) ((val) << (field ## _LSH))
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#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH))
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/*
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* Shift and width values for each register bitfield
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*/
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/* TMST_VALUE */
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#define TMST_VALUE_LSH 0
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#define TMST_VALUE_WID 8
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/* ENABLE */
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#define ACTIVE_LSH 7
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#define ACTIVE_WID 1
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#define STANDBY_LSH 6
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#define STANDBY_WID 1
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#define V3P3_SW_EN_LSH 5
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#define V3P3_SW_EN_WID 1
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#define VCOM_EN_LSH 4
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#define VCOM_EN_WID 1
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#define VDDH_EN_LSH 3
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#define VDDH_EN_WID 1
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#define VPOS_EN_LSH 2
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#define VPOS_EN_WID 1
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#define VEE_EN_LSH 1
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#define VEE_EN_WID 1
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#define VNEG_EN_LSH 0
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#define VNEG_EN_WID 1
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/* VCOM_ADJUST */
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#define VCOM_SET_LSH 0
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#define VCOM_SET_WID 8
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#define VCOM1_SET_LSH 0
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#define VCOM1_SET_WID 8
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#define VCOM2_SET_LSH 0
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#define VCOM2_SET_WID 1
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#define VCOM_ACQ_LSH 15
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#define VCOM_ACQ_WID 1
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#define VCOM_PROG_LSH 14
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#define VCOM_PEOG_WID 1
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#define VCOM_HiZ_LSH 13
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#define VCOM_HiZ_WID 1
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#define VCOM_AVG_LSH 11
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#define VCOM_AVG_WID 2
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/* INT_ENABLE1 */
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#define TSD_EN_LSH 6
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#define TSD_EN_WID 1
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#define HOT_EN_LSH 5
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#define HOT_EN_WID 1
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#define TMST_HOT_EN_LSH 4
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#define TMST_HOT_EN_WID 1
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#define TMST_COOL_EN_LSH 3
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#define TMST_COOL_EN_WID 1
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#define UVLO_EN_LSH 2
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#define UVLO_EN_WID 1
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/* INT_ENABLE2 */
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#define VB_UV_EN_LSH 7
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#define VB_UV_EN_WID 1
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#define VDDH_UV_EN_LSH 6
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#define VDDH_UV_EN_WID 1
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#define VN_UV_EN_LSH 5
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#define VN_UV_EN_WID 1
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#define VPOS_UV_EN_LSH 4
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#define VPOS_UV_EN_WID 1
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#define VEE_UV_EN_LSH 3
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#define VEE_UV_EN_WID 1
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#define VNEG_UV_EN_LSH 1
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#define VNEG_UV_EN_WID 1
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#define EOC_EN_LSH 0
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#define EOC_EN_WID 1
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/* INT_STATUS1 */
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#define TSDN_LSH 6
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#define TSDN_WID 1
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#define HOT_LSH 5
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#define HOT_WID 1
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#define TMST_HOT_LSH 4
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#define TMST_HOT_WID 1
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#define TMST_COOL_LSH 3
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#define TMST_COOL_WID 1
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#define UVLO_LSH 2
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#define UVLO_WID 1
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/* INT_STATUS2 */
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#define VB_UV_LSH 7
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#define VB_UV_WID 1
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#define VDDH_UV_LSH 6
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#define VDDH_UV_WID 1
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#define VN_UV_LSH 5
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#define VN_UV_WID 1
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#define VPOS_UV_LSH 4
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#define VPOS_UV_WID 1
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#define VEE_UV_LSH 3
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#define VEE_UV_WID 1
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#define VNEG_UV_LSH 1
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#define VNEG_UV_WID 1
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#define EOC_LSH 0
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#define EOC_WID 1
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/* PWR_SEQ0 */
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#define VDDH_SEQ_LSH 6
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#define VDDH_SEQ_WID 2
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#define VPOS_SEQ_LSH 4
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#define VPOS_SEQ_WID 2
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#define VEE_SEQ_LSH 2
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#define VEE_SEQ_WID 2
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#define VNEG_SEQ_LSH 0
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#define VNEG_SEQ_WID 2
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/* PWR_SEQ1 */
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#define DLY1_LSH 4
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#define DLY1_WID 4
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#define DLY0_LSH 0
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#define DLY0_WID 4
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/* PWR_SEQ2 */
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#define DLY3_LSH 4
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#define DLY3_WID 4
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#define DLY2_LSH 0
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#define DLY2_WID 4
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/* TMST_CONFIG */
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#define READ_THERM_LSH 7
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#define READ_THERM_WID 1
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#define CONV_END_LSH 5
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#define CONV_END_WID 1
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#define FAULT_QUE_LSH 3
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#define FAULT_QUE_WID 2
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#define FAULT_QUE_CLR_LSH 2
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#define FAULT_QUE_CLR_WID 1
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/* TMST_OS */
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#define TMST_HOT_SET_LSH 0
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#define TMST_HOT_SET_WID 8
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/* TMST_HYST */
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#define TMST_COOL_SET_LSH 0
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#define TMST_COOL_SET_WID 8
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/* PG_STATUS */
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#define VB_PG_LSH 7
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#define VB_PG_WID 1
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#define VDDH_PG_LSH 6
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#define VDDH_PG_WID 1
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#define VN_PG_LSH 5
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#define VN_PG_WID 1
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#define VPOS_PG_LSH 4
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#define VPOS_PG_WID 1
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#define VEE_PG_LSH 3
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#define VEE_PG_WID 1
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#define VNEG_PG_LSH 1
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#define VNEG_PG_WID 1
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/* REVID */
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#define MJREV_LSH 6
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#define MJREV_WID 2
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#define MNREV_LSH 4
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#define MNREV_WID 2
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#define VERSION_LSH 0
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#define VERSION_WID 4
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/* FIX_READ_POINTER */
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#define FIX_RD_PTR_LSH 0
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#define FIX_RD_PTR_WID 1
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/*
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* VCOM Definitions
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*
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* The register fields accept voltages in the range 0V to -2.75V, but the
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* VCOM parametric performance is only guaranteed from -0.3V to -2.5V.
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*/
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#define TPS65180_VCOM_MIN_uV -2750000
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#define TPS65180_VCOM_MAX_uV 0
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#define TPS65180_VCOM_MIN_SET 0
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#define TPS65180_VCOM_MAX_SET 255
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#define TPS65180_VCOM_BASE_uV 10740
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#define TPS65180_VCOM_STEP_uV 10740
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#define TPS65185_VCOM_MIN_uV -5110000
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#define TPS65185_VCOM_MAX_uV 0
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#define TPS65185_VCOM_MIN_SET 0
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#define TPS65185_VCOM_MAX_SET 511
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#define TPS65185_VCOM_BASE_uV 10000
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#define TPS65185_VCOM_STEP_uV 10000
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#define TPS6518x_VCOM_MIN_VAL 0
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#define TPS6518x_VCOM_MAX_VAL 255
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struct regulator_init_data;
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struct tps6518x {
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/* chip revision */
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int revID;
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struct device *dev;
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struct tps6518x_platform_data *pdata;
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/* Platform connection */
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struct i2c_client *i2c_client;
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/* Timings */
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unsigned int pwr_seq0;
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unsigned int pwr_seq1;
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unsigned int pwr_seq2;
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unsigned int upseq0;
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unsigned int upseq1;
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unsigned int dwnseq0;
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unsigned int dwnseq1;
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/* GPIOs */
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int gpio_pmic_pwrgood;
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int gpio_pmic_vcom_ctrl;
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int gpio_pmic_wakeup;
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int gpio_pmic_intr;
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int gpio_pmic_powerup;
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/* TPS6518x part variables */
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int pass_num;
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int vcom_uV;
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/* One-time VCOM setup marker */
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bool vcom_setup;
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/* powerup/powerdown wait time */
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int max_wait;
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/* Dynamically determined polarity for PWRGOOD */
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int pwrgood_polarity;
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};
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enum {
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/* In alphabetical order */
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TPS6518x_DISPLAY, /* virtual master enable */
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TPS6518x_VCOM,
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TPS6518x_V3P3,
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TPS6518x_NUM_REGULATORS,
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};
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/*
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* Declarations
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*/
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struct regulator_init_data;
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struct tps6518x_regulator_data;
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struct tps6518x_platform_data {
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unsigned int pwr_seq0;
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unsigned int pwr_seq1;
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unsigned int pwr_seq2;
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unsigned int upseq0;
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unsigned int upseq1;
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unsigned int dwnseq0;
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unsigned int dwnseq1;
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int gpio_pmic_pwrgood;
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int gpio_pmic_vcom_ctrl;
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int gpio_pmic_wakeup;
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int gpio_pmic_intr;
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int gpio_pmic_powerup;
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int pass_num;
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int vcom_uV;
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/* PMIC */
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struct tps6518x_regulator_data *regulators;
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int num_regulators;
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};
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struct tps6518x_regulator_data {
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int id;
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struct regulator_init_data *initdata;
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struct device_node *reg_node;
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};
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int tps6518x_reg_read(int reg_num, unsigned int *reg_val);
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int tps6518x_reg_write(int reg_num, const unsigned int reg_val);
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#endif
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