072f0a6338
On systems with mismatched i/d cache min line sizes, we need to use the smallest size possible across all CPUs. This will be done by fetching the system wide safe value from CPU feature infrastructure. However the some special users(e.g kexec, hibernate) would need the line size on the CPU (rather than the system wide), when either the system wide feature may not be accessible or it is guranteed that the caller executes with a gurantee of no migration. Provide another helper which will fetch cache line size on the current CPU. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Acked-by: James Morse <james.morse@arm.com> Reviewed-by: Geoff Levand <geoff@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
177 lines
5.2 KiB
ArmAsm
177 lines
5.2 KiB
ArmAsm
/*
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* Hibernate low-level support
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*
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* Copyright (C) 2016 ARM Ltd.
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* Author: James Morse <james.morse@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/errno.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <asm/cputype.h>
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#include <asm/memory.h>
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#include <asm/page.h>
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#include <asm/virt.h>
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/*
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* To prevent the possibility of old and new partial table walks being visible
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* in the tlb, switch the ttbr to a zero page when we invalidate the old
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* records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
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* Even switching to our copied tables will cause a changed output address at
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* each stage of the walk.
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*/
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.macro break_before_make_ttbr_switch zero_page, page_table
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msr ttbr1_el1, \zero_page
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isb
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tlbi vmalle1
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dsb nsh
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msr ttbr1_el1, \page_table
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isb
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.endm
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/*
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* Resume from hibernate
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*
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* Loads temporary page tables then restores the memory image.
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* Finally branches to cpu_resume() to restore the state saved by
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* swsusp_arch_suspend().
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*
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* Because this code has to be copied to a 'safe' page, it can't call out to
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* other functions by PC-relative address. Also remember that it may be
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* mid-way through over-writing other functions. For this reason it contains
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* code from flush_icache_range() and uses the copy_page() macro.
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*
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* This 'safe' page is mapped via ttbr0, and executed from there. This function
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* switches to a copy of the linear map in ttbr1, performs the restore, then
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* switches ttbr1 to the original kernel's swapper_pg_dir.
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*
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* All of memory gets written to, including code. We need to clean the kernel
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* text to the Point of Coherence (PoC) before secondary cores can be booted.
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* Because the kernel modules and executable pages mapped to user space are
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* also written as data, we clean all pages we touch to the Point of
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* Unification (PoU).
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*
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* x0: physical address of temporary page tables
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* x1: physical address of swapper page tables
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* x2: address of cpu_resume
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* x3: linear map address of restore_pblist in the current kernel
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* x4: physical address of __hyp_stub_vectors, or 0
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* x5: physical address of a zero page that remains zero after resume
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*/
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.pushsection ".hibernate_exit.text", "ax"
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ENTRY(swsusp_arch_suspend_exit)
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/*
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* We execute from ttbr0, change ttbr1 to our copied linear map tables
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* with a break-before-make via the zero page
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*/
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break_before_make_ttbr_switch x5, x0
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mov x21, x1
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mov x30, x2
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mov x24, x4
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mov x25, x5
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/* walk the restore_pblist and use copy_page() to over-write memory */
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mov x19, x3
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1: ldr x10, [x19, #HIBERN_PBE_ORIG]
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mov x0, x10
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ldr x1, [x19, #HIBERN_PBE_ADDR]
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copy_page x0, x1, x2, x3, x4, x5, x6, x7, x8, x9
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add x1, x10, #PAGE_SIZE
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/* Clean the copied page to PoU - based on flush_icache_range() */
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raw_dcache_line_size x2, x3
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sub x3, x2, #1
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bic x4, x10, x3
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2: dc cvau, x4 /* clean D line / unified line */
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add x4, x4, x2
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cmp x4, x1
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b.lo 2b
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ldr x19, [x19, #HIBERN_PBE_NEXT]
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cbnz x19, 1b
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dsb ish /* wait for PoU cleaning to finish */
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/* switch to the restored kernels page tables */
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break_before_make_ttbr_switch x25, x21
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ic ialluis
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dsb ish
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isb
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cbz x24, 3f /* Do we need to re-initialise EL2? */
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hvc #0
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3: ret
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.ltorg
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ENDPROC(swsusp_arch_suspend_exit)
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/*
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* Restore the hyp stub.
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* This must be done before the hibernate page is unmapped by _cpu_resume(),
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* but happens before any of the hyp-stub's code is cleaned to PoC.
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*
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* x24: The physical address of __hyp_stub_vectors
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*/
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el1_sync:
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msr vbar_el2, x24
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eret
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ENDPROC(el1_sync)
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.macro invalid_vector label
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\label:
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b \label
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ENDPROC(\label)
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.endm
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invalid_vector el2_sync_invalid
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invalid_vector el2_irq_invalid
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invalid_vector el2_fiq_invalid
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invalid_vector el2_error_invalid
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invalid_vector el1_sync_invalid
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invalid_vector el1_irq_invalid
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invalid_vector el1_fiq_invalid
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invalid_vector el1_error_invalid
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/* el2 vectors - switch el2 here while we restore the memory image. */
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.align 11
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ENTRY(hibernate_el2_vectors)
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ventry el2_sync_invalid // Synchronous EL2t
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ventry el2_irq_invalid // IRQ EL2t
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ventry el2_fiq_invalid // FIQ EL2t
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ventry el2_error_invalid // Error EL2t
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ventry el2_sync_invalid // Synchronous EL2h
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ventry el2_irq_invalid // IRQ EL2h
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ventry el2_fiq_invalid // FIQ EL2h
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ventry el2_error_invalid // Error EL2h
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ventry el1_sync // Synchronous 64-bit EL1
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ventry el1_irq_invalid // IRQ 64-bit EL1
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ventry el1_fiq_invalid // FIQ 64-bit EL1
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ventry el1_error_invalid // Error 64-bit EL1
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ventry el1_sync_invalid // Synchronous 32-bit EL1
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ventry el1_irq_invalid // IRQ 32-bit EL1
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ventry el1_fiq_invalid // FIQ 32-bit EL1
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ventry el1_error_invalid // Error 32-bit EL1
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END(hibernate_el2_vectors)
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.popsection
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