![Baoyou Xie](/assets/img/avatar_default.png)
We get 1 warning when building kernel with W=1: drivers/crypto/sunxi-ss/sun4i-ss-hash.c:168:5: warning: no previous prototype for 'sun4i_hash' [-Wmissing-prototypes] In fact, this function is only used in the file in which it is declared and don't need a declaration, but can be made static. So this patch marks it 'static'. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
522 lines
13 KiB
C
522 lines
13 KiB
C
/*
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* sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
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*
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* Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
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*
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* This file add support for MD5 and SHA1.
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*
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* You could find the datasheet in Documentation/arm/sunxi/README
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "sun4i-ss.h"
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#include <linux/scatterlist.h>
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/* This is a totally arbitrary value */
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#define SS_TIMEOUT 100
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int sun4i_hash_crainit(struct crypto_tfm *tfm)
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{
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struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm);
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struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
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struct sun4i_ss_alg_template *algt;
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memset(op, 0, sizeof(struct sun4i_tfm_ctx));
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algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
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op->ss = algt->ss;
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crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
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sizeof(struct sun4i_req_ctx));
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return 0;
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}
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/* sun4i_hash_init: initialize request context */
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int sun4i_hash_init(struct ahash_request *areq)
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{
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struct sun4i_req_ctx *op = ahash_request_ctx(areq);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
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struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
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struct sun4i_ss_alg_template *algt;
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memset(op, 0, sizeof(struct sun4i_req_ctx));
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algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
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op->mode = algt->mode;
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return 0;
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}
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int sun4i_hash_export_md5(struct ahash_request *areq, void *out)
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{
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struct sun4i_req_ctx *op = ahash_request_ctx(areq);
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struct md5_state *octx = out;
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int i;
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octx->byte_count = op->byte_count + op->len;
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memcpy(octx->block, op->buf, op->len);
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if (op->byte_count > 0) {
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for (i = 0; i < 4; i++)
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octx->hash[i] = op->hash[i];
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} else {
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octx->hash[0] = SHA1_H0;
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octx->hash[1] = SHA1_H1;
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octx->hash[2] = SHA1_H2;
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octx->hash[3] = SHA1_H3;
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}
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return 0;
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}
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int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
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{
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struct sun4i_req_ctx *op = ahash_request_ctx(areq);
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const struct md5_state *ictx = in;
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int i;
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sun4i_hash_init(areq);
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op->byte_count = ictx->byte_count & ~0x3F;
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op->len = ictx->byte_count & 0x3F;
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memcpy(op->buf, ictx->block, op->len);
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for (i = 0; i < 4; i++)
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op->hash[i] = ictx->hash[i];
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return 0;
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}
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int sun4i_hash_export_sha1(struct ahash_request *areq, void *out)
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{
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struct sun4i_req_ctx *op = ahash_request_ctx(areq);
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struct sha1_state *octx = out;
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int i;
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octx->count = op->byte_count + op->len;
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memcpy(octx->buffer, op->buf, op->len);
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if (op->byte_count > 0) {
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for (i = 0; i < 5; i++)
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octx->state[i] = op->hash[i];
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} else {
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octx->state[0] = SHA1_H0;
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octx->state[1] = SHA1_H1;
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octx->state[2] = SHA1_H2;
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octx->state[3] = SHA1_H3;
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octx->state[4] = SHA1_H4;
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}
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return 0;
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}
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int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in)
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{
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struct sun4i_req_ctx *op = ahash_request_ctx(areq);
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const struct sha1_state *ictx = in;
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int i;
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sun4i_hash_init(areq);
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op->byte_count = ictx->count & ~0x3F;
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op->len = ictx->count & 0x3F;
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memcpy(op->buf, ictx->buffer, op->len);
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for (i = 0; i < 5; i++)
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op->hash[i] = ictx->state[i];
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return 0;
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}
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#define SS_HASH_UPDATE 1
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#define SS_HASH_FINAL 2
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/*
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* sun4i_hash_update: update hash engine
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*
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* Could be used for both SHA1 and MD5
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* Write data by step of 32bits and put then in the SS.
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*
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* Since we cannot leave partial data and hash state in the engine,
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* we need to get the hash state at the end of this function.
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* We can get the hash state every 64 bytes
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*
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* So the first work is to get the number of bytes to write to SS modulo 64
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* The extra bytes will go to a temporary buffer op->buf storing op->len bytes
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*
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* So at the begin of update()
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* if op->len + areq->nbytes < 64
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* => all data will be written to wait buffer (op->buf) and end=0
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* if not, write all data from op->buf to the device and position end to
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* complete to 64bytes
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*
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* example 1:
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* update1 60o => op->len=60
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* update2 60o => need one more word to have 64 bytes
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* end=4
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* so write all data from op->buf and one word of SGs
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* write remaining data in op->buf
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* final state op->len=56
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*/
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static int sun4i_hash(struct ahash_request *areq)
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{
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u32 v, ivmode = 0;
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unsigned int i = 0;
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/*
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* i is the total bytes read from SGs, to be compared to areq->nbytes
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* i is important because we cannot rely on SG length since the sum of
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* SG->length could be greater than areq->nbytes
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*/
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struct sun4i_req_ctx *op = ahash_request_ctx(areq);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
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struct sun4i_tfm_ctx *tfmctx = crypto_ahash_ctx(tfm);
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struct sun4i_ss_ctx *ss = tfmctx->ss;
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unsigned int in_i = 0; /* advancement in the current SG */
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unsigned int end;
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/*
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* end is the position when we need to stop writing to the device,
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* to be compared to i
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*/
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int in_r, err = 0;
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unsigned int todo;
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u32 spaces, rx_cnt = SS_RX_DEFAULT;
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size_t copied = 0;
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struct sg_mapping_iter mi;
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unsigned int j = 0;
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int zeros;
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unsigned int index, padlen;
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__be64 bits;
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u32 bf[32];
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u32 wb = 0;
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unsigned int nwait, nbw = 0;
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struct scatterlist *in_sg = areq->src;
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dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x wl=%u h0=%0x",
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__func__, crypto_tfm_alg_name(areq->base.tfm),
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op->byte_count, areq->nbytes, op->mode,
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op->len, op->hash[0]);
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if (unlikely(areq->nbytes == 0) && (op->flags & SS_HASH_FINAL) == 0)
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return 0;
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/* protect against overflow */
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if (unlikely(areq->nbytes > UINT_MAX - op->len)) {
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dev_err(ss->dev, "Cannot process too large request\n");
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return -EINVAL;
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}
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if (op->len + areq->nbytes < 64 && (op->flags & SS_HASH_FINAL) == 0) {
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/* linearize data to op->buf */
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copied = sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
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op->buf + op->len, areq->nbytes, 0);
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op->len += copied;
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return 0;
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}
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spin_lock_bh(&ss->slock);
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/*
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* if some data have been processed before,
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* we need to restore the partial hash state
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*/
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if (op->byte_count > 0) {
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ivmode = SS_IV_ARBITRARY;
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for (i = 0; i < 5; i++)
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writel(op->hash[i], ss->base + SS_IV0 + i * 4);
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}
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/* Enable the device */
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writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
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if ((op->flags & SS_HASH_UPDATE) == 0)
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goto hash_final;
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/* start of handling data */
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if ((op->flags & SS_HASH_FINAL) == 0) {
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end = ((areq->nbytes + op->len) / 64) * 64 - op->len;
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if (end > areq->nbytes || areq->nbytes - end > 63) {
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dev_err(ss->dev, "ERROR: Bound error %u %u\n",
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end, areq->nbytes);
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err = -EINVAL;
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goto release_ss;
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}
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} else {
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/* Since we have the flag final, we can go up to modulo 4 */
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end = ((areq->nbytes + op->len) / 4) * 4 - op->len;
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}
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/* TODO if SGlen % 4 and op->len == 0 then DMA */
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i = 1;
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while (in_sg && i == 1) {
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if ((in_sg->length % 4) != 0)
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i = 0;
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in_sg = sg_next(in_sg);
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}
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if (i == 1 && op->len == 0)
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dev_dbg(ss->dev, "We can DMA\n");
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i = 0;
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sg_miter_start(&mi, areq->src, sg_nents(areq->src),
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SG_MITER_FROM_SG | SG_MITER_ATOMIC);
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sg_miter_next(&mi);
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in_i = 0;
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do {
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/*
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* we need to linearize in two case:
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* - the buffer is already used
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* - the SG does not have enough byte remaining ( < 4)
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*/
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if (op->len > 0 || (mi.length - in_i) < 4) {
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/*
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* if we have entered here we have two reason to stop
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* - the buffer is full
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* - reach the end
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*/
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while (op->len < 64 && i < end) {
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/* how many bytes we can read from current SG */
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in_r = min3(mi.length - in_i, end - i,
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64 - op->len);
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memcpy(op->buf + op->len, mi.addr + in_i, in_r);
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op->len += in_r;
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i += in_r;
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in_i += in_r;
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if (in_i == mi.length) {
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sg_miter_next(&mi);
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in_i = 0;
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}
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}
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if (op->len > 3 && (op->len % 4) == 0) {
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/* write buf to the device */
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writesl(ss->base + SS_RXFIFO, op->buf,
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op->len / 4);
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op->byte_count += op->len;
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op->len = 0;
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}
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}
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if (mi.length - in_i > 3 && i < end) {
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/* how many bytes we can read from current SG */
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in_r = min3(mi.length - in_i, areq->nbytes - i,
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((mi.length - in_i) / 4) * 4);
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/* how many bytes we can write in the device*/
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todo = min3((u32)(end - i) / 4, rx_cnt, (u32)in_r / 4);
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writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo);
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op->byte_count += todo * 4;
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i += todo * 4;
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in_i += todo * 4;
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rx_cnt -= todo;
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if (rx_cnt == 0) {
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spaces = readl(ss->base + SS_FCSR);
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rx_cnt = SS_RXFIFO_SPACES(spaces);
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}
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if (in_i == mi.length) {
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sg_miter_next(&mi);
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in_i = 0;
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}
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}
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} while (i < end);
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/*
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* Now we have written to the device all that we can,
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* store the remaining bytes in op->buf
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*/
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if ((areq->nbytes - i) < 64) {
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while (i < areq->nbytes && in_i < mi.length && op->len < 64) {
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/* how many bytes we can read from current SG */
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in_r = min3(mi.length - in_i, areq->nbytes - i,
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64 - op->len);
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memcpy(op->buf + op->len, mi.addr + in_i, in_r);
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op->len += in_r;
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i += in_r;
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in_i += in_r;
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if (in_i == mi.length) {
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sg_miter_next(&mi);
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in_i = 0;
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}
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}
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}
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sg_miter_stop(&mi);
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/*
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* End of data process
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* Now if we have the flag final go to finalize part
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* If not, store the partial hash
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*/
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if ((op->flags & SS_HASH_FINAL) > 0)
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goto hash_final;
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writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
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i = 0;
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do {
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v = readl(ss->base + SS_CTL);
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i++;
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} while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
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if (unlikely(i >= SS_TIMEOUT)) {
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dev_err_ratelimited(ss->dev,
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"ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
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i, SS_TIMEOUT, v, areq->nbytes);
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err = -EIO;
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goto release_ss;
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}
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for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++)
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op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
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goto release_ss;
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/*
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* hash_final: finalize hashing operation
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*
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* If we have some remaining bytes, we write them.
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* Then ask the SS for finalizing the hashing operation
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*
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* I do not check RX FIFO size in this function since the size is 32
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* after each enabling and this function neither write more than 32 words.
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* If we come from the update part, we cannot have more than
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* 3 remaining bytes to write and SS is fast enough to not care about it.
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*/
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hash_final:
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/* write the remaining words of the wait buffer */
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if (op->len > 0) {
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nwait = op->len / 4;
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if (nwait > 0) {
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writesl(ss->base + SS_RXFIFO, op->buf, nwait);
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op->byte_count += 4 * nwait;
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}
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nbw = op->len - 4 * nwait;
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wb = *(u32 *)(op->buf + nwait * 4);
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wb &= (0xFFFFFFFF >> (4 - nbw) * 8);
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}
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/* write the remaining bytes of the nbw buffer */
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if (nbw > 0) {
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wb |= ((1 << 7) << (nbw * 8));
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bf[j++] = wb;
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} else {
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bf[j++] = 1 << 7;
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}
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/*
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* number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
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* I take the operations from other MD5/SHA1 implementations
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*/
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/* we have already send 4 more byte of which nbw data */
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if (op->mode == SS_OP_MD5) {
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index = (op->byte_count + 4) & 0x3f;
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op->byte_count += nbw;
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if (index > 56)
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zeros = (120 - index) / 4;
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else
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zeros = (56 - index) / 4;
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} else {
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op->byte_count += nbw;
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index = op->byte_count & 0x3f;
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padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
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zeros = (padlen - 1) / 4;
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}
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memset(bf + j, 0, 4 * zeros);
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j += zeros;
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/* write the length of data */
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if (op->mode == SS_OP_SHA1) {
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bits = cpu_to_be64(op->byte_count << 3);
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bf[j++] = bits & 0xffffffff;
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bf[j++] = (bits >> 32) & 0xffffffff;
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} else {
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bf[j++] = (op->byte_count << 3) & 0xffffffff;
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bf[j++] = (op->byte_count >> 29) & 0xffffffff;
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}
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writesl(ss->base + SS_RXFIFO, bf, j);
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/* Tell the SS to stop the hashing */
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writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
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/*
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* Wait for SS to finish the hash.
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* The timeout could happen only in case of bad overclocking
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* or driver bug.
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*/
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i = 0;
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do {
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v = readl(ss->base + SS_CTL);
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i++;
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} while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
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if (unlikely(i >= SS_TIMEOUT)) {
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dev_err_ratelimited(ss->dev,
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"ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
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i, SS_TIMEOUT, v, areq->nbytes);
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err = -EIO;
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goto release_ss;
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}
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/* Get the hash from the device */
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if (op->mode == SS_OP_SHA1) {
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for (i = 0; i < 5; i++) {
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v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
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memcpy(areq->result + i * 4, &v, 4);
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}
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} else {
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for (i = 0; i < 4; i++) {
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v = readl(ss->base + SS_MD0 + i * 4);
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memcpy(areq->result + i * 4, &v, 4);
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}
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}
|
|
|
|
release_ss:
|
|
writel(0, ss->base + SS_CTL);
|
|
spin_unlock_bh(&ss->slock);
|
|
return err;
|
|
}
|
|
|
|
int sun4i_hash_final(struct ahash_request *areq)
|
|
{
|
|
struct sun4i_req_ctx *op = ahash_request_ctx(areq);
|
|
|
|
op->flags = SS_HASH_FINAL;
|
|
return sun4i_hash(areq);
|
|
}
|
|
|
|
int sun4i_hash_update(struct ahash_request *areq)
|
|
{
|
|
struct sun4i_req_ctx *op = ahash_request_ctx(areq);
|
|
|
|
op->flags = SS_HASH_UPDATE;
|
|
return sun4i_hash(areq);
|
|
}
|
|
|
|
/* sun4i_hash_finup: finalize hashing operation after an update */
|
|
int sun4i_hash_finup(struct ahash_request *areq)
|
|
{
|
|
struct sun4i_req_ctx *op = ahash_request_ctx(areq);
|
|
|
|
op->flags = SS_HASH_UPDATE | SS_HASH_FINAL;
|
|
return sun4i_hash(areq);
|
|
}
|
|
|
|
/* combo of init/update/final functions */
|
|
int sun4i_hash_digest(struct ahash_request *areq)
|
|
{
|
|
int err;
|
|
struct sun4i_req_ctx *op = ahash_request_ctx(areq);
|
|
|
|
err = sun4i_hash_init(areq);
|
|
if (err != 0)
|
|
return err;
|
|
|
|
op->flags = SS_HASH_UPDATE | SS_HASH_FINAL;
|
|
return sun4i_hash(areq);
|
|
}
|