4dfc050571
Our GICv3 emulation always presents ICC_SRE_EL1 with DIB/DFB set to zero, which implies that there is a way to bypass the GIC and inject raw IRQ/FIQ by driving the CPU pins. Of course, we don't allow that when the GIC is configured, but we fail to indicate that to the guest. The obvious fix is to set these bits (and never let them being changed again). Reported-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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| .. | ||
| arm-gic-common.h | ||
| arm-gic-v3.h | ||
| arm-gic.h | ||
| arm-vic.h | ||
| chained_irq.h | ||
| ingenic.h | ||
| irq-omap-intc.h | ||
| irq-partition-percpu.h | ||
| irq-sa11x0.h | ||
| metag-ext.h | ||
| metag.h | ||
| mips-gic.h | ||
| mmp.h | ||
| mxs.h | ||
| versatile-fpga.h | ||
| xtensa-mx.h | ||
| xtensa-pic.h | ||