df3305156f
Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that models a video pipeline described in the device tree and expose the pipeline to userspace through the media controller and V4L2 APIs. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* Xilinx Video IP Core
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*
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* Copyright (C) 2013-2015 Ideas on Board
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* Copyright (C) 2013-2015 Xilinx, Inc.
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*
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* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__
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#define __DT_BINDINGS_MEDIA_XILINX_VIP_H__
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/*
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* Video format codes as defined in "AXI4-Stream Video IP and System Design
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* Guide".
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*/
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#define XVIP_VF_YUV_422 0
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#define XVIP_VF_YUV_444 1
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#define XVIP_VF_RBG 2
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#define XVIP_VF_YUV_420 3
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#define XVIP_VF_YUVA_422 4
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#define XVIP_VF_YUVA_444 5
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#define XVIP_VF_RGBA 6
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#define XVIP_VF_YUVA_420 7
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#define XVIP_VF_YUVD_422 8
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#define XVIP_VF_YUVD_444 9
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#define XVIP_VF_RGBD 10
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#define XVIP_VF_YUVD_420 11
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#define XVIP_VF_MONO_SENSOR 12
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#define XVIP_VF_CUSTOM2 13
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#define XVIP_VF_CUSTOM3 14
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#define XVIP_VF_CUSTOM4 15
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#endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */
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