93fbe91b55
Timers IPs can be used to generate triggers for other IPs like DAC or ADC. Each trigger may result of timer internals signals like counter enable, reset or edge, this configuration could be done through "master_mode" device attribute. Since triggers could be used by DAC or ADC their names are defined in include/ nux/iio/timer/stm32-timer-trigger.h and is_stm32_iio_timer_trigger function could be used to check if the trigger is valid or not. "trgo" trigger have a "sampling_frequency" attribute which allow to configure timer sampling frequency. version 8: - change kernel version from 4.10 to 4.11 in ABI documentation version 7: - remove all iio_device related code - move driver into trigger directory version 5: - simplify tables of triggers - only create an IIO device when needed version 4: - get triggers configuration from "reg" in DT - add tables of triggers - sampling frequency is enable/disable when writing in trigger sampling_frequency attribute - no more use of interruptions version 3: - change compatible to "st,stm32-timer-trigger" - fix attributes access right - use string instead of int for master_mode and slave_mode - document device attributes in sysfs-bus-iio-timer-stm32 version 2: - keep only one compatible - use st,input-triggers-names and st,output-triggers-names to know which triggers are accepted and/or create by the device Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
/*
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* Copyright (C) STMicroelectronics 2016
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*
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* Author: Benjamin Gaignard <benjamin.gaignard@st.com>
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*
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* License terms: GNU General Public License (GPL), version 2
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*/
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#ifndef _STM32_TIMER_TRIGGER_H_
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#define _STM32_TIMER_TRIGGER_H_
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#define TIM1_TRGO "tim1_trgo"
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#define TIM1_CH1 "tim1_ch1"
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#define TIM1_CH2 "tim1_ch2"
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#define TIM1_CH3 "tim1_ch3"
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#define TIM1_CH4 "tim1_ch4"
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#define TIM2_TRGO "tim2_trgo"
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#define TIM2_CH1 "tim2_ch1"
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#define TIM2_CH2 "tim2_ch2"
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#define TIM2_CH3 "tim2_ch3"
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#define TIM2_CH4 "tim2_ch4"
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#define TIM3_TRGO "tim3_trgo"
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#define TIM3_CH1 "tim3_ch1"
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#define TIM3_CH2 "tim3_ch2"
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#define TIM3_CH3 "tim3_ch3"
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#define TIM3_CH4 "tim3_ch4"
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#define TIM4_TRGO "tim4_trgo"
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#define TIM4_CH1 "tim4_ch1"
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#define TIM4_CH2 "tim4_ch2"
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#define TIM4_CH3 "tim4_ch3"
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#define TIM4_CH4 "tim4_ch4"
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#define TIM5_TRGO "tim5_trgo"
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#define TIM5_CH1 "tim5_ch1"
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#define TIM5_CH2 "tim5_ch2"
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#define TIM5_CH3 "tim5_ch3"
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#define TIM5_CH4 "tim5_ch4"
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#define TIM6_TRGO "tim6_trgo"
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#define TIM7_TRGO "tim7_trgo"
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#define TIM8_TRGO "tim8_trgo"
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#define TIM8_CH1 "tim8_ch1"
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#define TIM8_CH2 "tim8_ch2"
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#define TIM8_CH3 "tim8_ch3"
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#define TIM8_CH4 "tim8_ch4"
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#define TIM9_TRGO "tim9_trgo"
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#define TIM9_CH1 "tim9_ch1"
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#define TIM9_CH2 "tim9_ch2"
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#define TIM12_TRGO "tim12_trgo"
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#define TIM12_CH1 "tim12_ch1"
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#define TIM12_CH2 "tim12_ch2"
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bool is_stm32_timer_trigger(struct iio_trigger *trig);
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#endif
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