![Adrian Bunk](/assets/img/avatar_default.png)
Once upon a time, the MTD repository was using CVS. This patch therefore removes all usages of the no longer updated CVS keywords from the MTD code. This also includes code that printed them to the user. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
496 lines
13 KiB
C
496 lines
13 KiB
C
/* dilnetpc.c -- MTD map driver for SSV DIL/Net PC Boards "DNP" and "ADNP"
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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* The DIL/Net PC is a tiny embedded PC board made by SSV Embedded Systems
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* featuring the AMD Elan SC410 processor. There are two variants of this
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* board: DNP/1486 and ADNP/1486. The DNP version has 2 megs of flash
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* ROM (Intel 28F016S3) and 8 megs of DRAM, the ADNP version has 4 megs
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* flash and 16 megs of RAM.
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* For details, see http://www.ssv-embedded.de/ssv/pc104/p169.htm
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* and http://www.ssv-embedded.de/ssv/pc104/p170.htm
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/concat.h>
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#include <asm/io.h>
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/*
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** The DIL/NetPC keeps its BIOS in two distinct flash blocks.
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** Destroying any of these blocks transforms the DNPC into
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** a paperweight (albeit not a very useful one, considering
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** it only weighs a few grams).
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**
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** Therefore, the BIOS blocks must never be erased or written to
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** except by people who know exactly what they are doing (e.g.
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** to install a BIOS update). These partitions are marked read-only
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** by default, but can be made read/write by undefining
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** DNPC_BIOS_BLOCKS_WRITEPROTECTED:
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*/
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#define DNPC_BIOS_BLOCKS_WRITEPROTECTED
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/*
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** The ID string (in ROM) is checked to determine whether we
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** are running on a DNP/1486 or ADNP/1486
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*/
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#define BIOSID_BASE 0x000fe100
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#define ID_DNPC "DNP1486"
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#define ID_ADNP "ADNP1486"
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/*
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** Address where the flash should appear in CPU space
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*/
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#define FLASH_BASE 0x2000000
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/*
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** Chip Setup and Control (CSC) indexed register space
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*/
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#define CSC_INDEX 0x22
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#define CSC_DATA 0x23
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#define CSC_MMSWAR 0x30 /* MMS window C-F attributes register */
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#define CSC_MMSWDSR 0x31 /* MMS window C-F device select register */
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#define CSC_RBWR 0xa7 /* GPIO Read-Back/Write Register B */
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#define CSC_CR 0xd0 /* internal I/O device disable/Echo */
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/* Z-bus/configuration register */
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#define CSC_PCCMDCR 0xf1 /* PC card mode and DMA control register */
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/*
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** PC Card indexed register space:
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*/
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#define PCC_INDEX 0x3e0
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#define PCC_DATA 0x3e1
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#define PCC_AWER_B 0x46 /* Socket B Address Window enable register */
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#define PCC_MWSAR_1_Lo 0x58 /* memory window 1 start address low register */
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#define PCC_MWSAR_1_Hi 0x59 /* memory window 1 start address high register */
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#define PCC_MWEAR_1_Lo 0x5A /* memory window 1 stop address low register */
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#define PCC_MWEAR_1_Hi 0x5B /* memory window 1 stop address high register */
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#define PCC_MWAOR_1_Lo 0x5C /* memory window 1 address offset low register */
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#define PCC_MWAOR_1_Hi 0x5D /* memory window 1 address offset high register */
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/*
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** Access to SC4x0's Chip Setup and Control (CSC)
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** and PC Card (PCC) indexed registers:
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*/
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static inline void setcsc(int reg, unsigned char data)
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{
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outb(reg, CSC_INDEX);
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outb(data, CSC_DATA);
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}
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static inline unsigned char getcsc(int reg)
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{
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outb(reg, CSC_INDEX);
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return(inb(CSC_DATA));
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}
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static inline void setpcc(int reg, unsigned char data)
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{
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outb(reg, PCC_INDEX);
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outb(data, PCC_DATA);
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}
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static inline unsigned char getpcc(int reg)
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{
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outb(reg, PCC_INDEX);
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return(inb(PCC_DATA));
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}
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/*
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************************************************************
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** Enable access to DIL/NetPC's flash by mapping it into
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** the SC4x0's MMS Window C.
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************************************************************
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*/
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static void dnpc_map_flash(unsigned long flash_base, unsigned long flash_size)
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{
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unsigned long flash_end = flash_base + flash_size - 1;
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/*
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** enable setup of MMS windows C-F:
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*/
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/* - enable PC Card indexed register space */
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setcsc(CSC_CR, getcsc(CSC_CR) | 0x2);
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/* - set PC Card controller to operate in standard mode */
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setcsc(CSC_PCCMDCR, getcsc(CSC_PCCMDCR) & ~1);
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/*
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** Program base address and end address of window
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** where the flash ROM should appear in CPU address space
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*/
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setpcc(PCC_MWSAR_1_Lo, (flash_base >> 12) & 0xff);
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setpcc(PCC_MWSAR_1_Hi, (flash_base >> 20) & 0x3f);
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setpcc(PCC_MWEAR_1_Lo, (flash_end >> 12) & 0xff);
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setpcc(PCC_MWEAR_1_Hi, (flash_end >> 20) & 0x3f);
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/* program offset of first flash location to appear in this window (0) */
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setpcc(PCC_MWAOR_1_Lo, ((0 - flash_base) >> 12) & 0xff);
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setpcc(PCC_MWAOR_1_Hi, ((0 - flash_base)>> 20) & 0x3f);
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/* set attributes for MMS window C: non-cacheable, write-enabled */
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setcsc(CSC_MMSWAR, getcsc(CSC_MMSWAR) & ~0x11);
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/* select physical device ROMCS0 (i.e. flash) for MMS Window C */
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setcsc(CSC_MMSWDSR, getcsc(CSC_MMSWDSR) & ~0x03);
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/* enable memory window 1 */
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setpcc(PCC_AWER_B, getpcc(PCC_AWER_B) | 0x02);
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/* now disable PC Card indexed register space again */
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setcsc(CSC_CR, getcsc(CSC_CR) & ~0x2);
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}
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/*
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************************************************************
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** Disable access to DIL/NetPC's flash by mapping it into
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** the SC4x0's MMS Window C.
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************************************************************
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*/
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static void dnpc_unmap_flash(void)
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{
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/* - enable PC Card indexed register space */
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setcsc(CSC_CR, getcsc(CSC_CR) | 0x2);
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/* disable memory window 1 */
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setpcc(PCC_AWER_B, getpcc(PCC_AWER_B) & ~0x02);
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/* now disable PC Card indexed register space again */
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setcsc(CSC_CR, getcsc(CSC_CR) & ~0x2);
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}
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/*
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************************************************************
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** Enable/Disable VPP to write to flash
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************************************************************
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*/
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static DEFINE_SPINLOCK(dnpc_spin);
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static int vpp_counter = 0;
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/*
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** This is what has to be done for the DNP board ..
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*/
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static void dnp_set_vpp(struct map_info *not_used, int on)
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{
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spin_lock_irq(&dnpc_spin);
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if (on)
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{
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if(++vpp_counter == 1)
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setcsc(CSC_RBWR, getcsc(CSC_RBWR) & ~0x4);
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}
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else
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{
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if(--vpp_counter == 0)
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setcsc(CSC_RBWR, getcsc(CSC_RBWR) | 0x4);
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else
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BUG_ON(vpp_counter < 0);
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}
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spin_unlock_irq(&dnpc_spin);
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}
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/*
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** .. and this the ADNP version:
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*/
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static void adnp_set_vpp(struct map_info *not_used, int on)
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{
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spin_lock_irq(&dnpc_spin);
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if (on)
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{
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if(++vpp_counter == 1)
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setcsc(CSC_RBWR, getcsc(CSC_RBWR) & ~0x8);
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}
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else
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{
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if(--vpp_counter == 0)
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setcsc(CSC_RBWR, getcsc(CSC_RBWR) | 0x8);
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else
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BUG_ON(vpp_counter < 0);
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}
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spin_unlock_irq(&dnpc_spin);
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}
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#define DNP_WINDOW_SIZE 0x00200000 /* DNP flash size is 2MiB */
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#define ADNP_WINDOW_SIZE 0x00400000 /* ADNP flash size is 4MiB */
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#define WINDOW_ADDR FLASH_BASE
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static struct map_info dnpc_map = {
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.name = "ADNP Flash Bank",
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.size = ADNP_WINDOW_SIZE,
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.bankwidth = 1,
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.set_vpp = adnp_set_vpp,
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.phys = WINDOW_ADDR
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};
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/*
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** The layout of the flash is somewhat "strange":
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**
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** 1. 960 KiB (15 blocks) : Space for ROM Bootloader and user data
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** 2. 64 KiB (1 block) : System BIOS
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** 3. 960 KiB (15 blocks) : User Data (DNP model) or
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** 3. 3008 KiB (47 blocks) : User Data (ADNP model)
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** 4. 64 KiB (1 block) : System BIOS Entry
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*/
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static struct mtd_partition partition_info[]=
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{
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{
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.name = "ADNP boot",
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.offset = 0,
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.size = 0xf0000,
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},
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{
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.name = "ADNP system BIOS",
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.offset = MTDPART_OFS_NXTBLK,
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.size = 0x10000,
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#ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
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.mask_flags = MTD_WRITEABLE,
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#endif
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},
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{
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.name = "ADNP file system",
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.offset = MTDPART_OFS_NXTBLK,
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.size = 0x2f0000,
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},
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{
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.name = "ADNP system BIOS entry",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL,
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#ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
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.mask_flags = MTD_WRITEABLE,
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#endif
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},
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};
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#define NUM_PARTITIONS ARRAY_SIZE(partition_info)
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static struct mtd_info *mymtd;
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static struct mtd_info *lowlvl_parts[NUM_PARTITIONS];
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static struct mtd_info *merged_mtd;
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/*
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** "Highlevel" partition info:
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**
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** Using the MTD concat layer, we can re-arrange partitions to our
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** liking: we construct a virtual MTD device by concatenating the
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** partitions, specifying the sequence such that the boot block
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** is immediately followed by the filesystem block (i.e. the stupid
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** system BIOS block is mapped to a different place). When re-partitioning
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** this concatenated MTD device, we can set the boot block size to
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** an arbitrary (though erase block aligned) value i.e. not one that
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** is dictated by the flash's physical layout. We can thus set the
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** boot block to be e.g. 64 KB (which is fully sufficient if we want
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** to boot an etherboot image) or to -say- 1.5 MB if we want to boot
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** a large kernel image. In all cases, the remainder of the flash
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** is available as file system space.
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*/
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static struct mtd_partition higlvl_partition_info[]=
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{
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{
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.name = "ADNP boot block",
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.offset = 0,
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.size = CONFIG_MTD_DILNETPC_BOOTSIZE,
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},
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{
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.name = "ADNP file system space",
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.offset = MTDPART_OFS_NXTBLK,
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.size = ADNP_WINDOW_SIZE-CONFIG_MTD_DILNETPC_BOOTSIZE-0x20000,
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},
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{
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.name = "ADNP system BIOS + BIOS Entry",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL,
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#ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
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.mask_flags = MTD_WRITEABLE,
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#endif
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},
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};
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#define NUM_HIGHLVL_PARTITIONS ARRAY_SIZE(higlvl_partition_info)
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static int dnp_adnp_probe(void)
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{
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char *biosid, rc = -1;
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biosid = (char*)ioremap(BIOSID_BASE, 16);
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if(biosid)
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{
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if(!strcmp(biosid, ID_DNPC))
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rc = 1; /* this is a DNPC */
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else if(!strcmp(biosid, ID_ADNP))
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rc = 0; /* this is a ADNPC */
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}
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iounmap((void *)biosid);
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return(rc);
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}
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static int __init init_dnpc(void)
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{
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int is_dnp;
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/*
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** determine hardware (DNP/ADNP/invalid)
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*/
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if((is_dnp = dnp_adnp_probe()) < 0)
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return -ENXIO;
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/*
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** Things are set up for ADNP by default
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** -> modify all that needs to be different for DNP
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*/
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if(is_dnp)
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{ /*
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** Adjust window size, select correct set_vpp function.
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** The partitioning scheme is identical on both DNP
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** and ADNP except for the size of the third partition.
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*/
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int i;
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dnpc_map.size = DNP_WINDOW_SIZE;
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dnpc_map.set_vpp = dnp_set_vpp;
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partition_info[2].size = 0xf0000;
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/*
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** increment all string pointers so the leading 'A' gets skipped,
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** thus turning all occurrences of "ADNP ..." into "DNP ..."
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*/
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++dnpc_map.name;
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for(i = 0; i < NUM_PARTITIONS; i++)
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++partition_info[i].name;
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higlvl_partition_info[1].size = DNP_WINDOW_SIZE -
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CONFIG_MTD_DILNETPC_BOOTSIZE - 0x20000;
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for(i = 0; i < NUM_HIGHLVL_PARTITIONS; i++)
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++higlvl_partition_info[i].name;
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}
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printk(KERN_NOTICE "DIL/Net %s flash: 0x%lx at 0x%llx\n",
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is_dnp ? "DNPC" : "ADNP", dnpc_map.size, (unsigned long long)dnpc_map.phys);
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dnpc_map.virt = ioremap_nocache(dnpc_map.phys, dnpc_map.size);
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dnpc_map_flash(dnpc_map.phys, dnpc_map.size);
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if (!dnpc_map.virt) {
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printk("Failed to ioremap_nocache\n");
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return -EIO;
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}
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simple_map_init(&dnpc_map);
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printk("FLASH virtual address: 0x%p\n", dnpc_map.virt);
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mymtd = do_map_probe("jedec_probe", &dnpc_map);
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if (!mymtd)
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mymtd = do_map_probe("cfi_probe", &dnpc_map);
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/*
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** If flash probes fail, try to make flashes accessible
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** at least as ROM. Ajust erasesize in this case since
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** the default one (128M) will break our partitioning
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*/
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if (!mymtd)
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if((mymtd = do_map_probe("map_rom", &dnpc_map)))
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mymtd->erasesize = 0x10000;
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if (!mymtd) {
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iounmap(dnpc_map.virt);
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return -ENXIO;
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}
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mymtd->owner = THIS_MODULE;
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/*
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** Supply pointers to lowlvl_parts[] array to add_mtd_partitions()
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** -> add_mtd_partitions() will _not_ register MTD devices for
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** the partitions, but will instead store pointers to the MTD
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** objects it creates into our lowlvl_parts[] array.
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** NOTE: we arrange the pointers such that the sequence of the
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** partitions gets re-arranged: partition #2 follows
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** partition #0.
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*/
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partition_info[0].mtdp = &lowlvl_parts[0];
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partition_info[1].mtdp = &lowlvl_parts[2];
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partition_info[2].mtdp = &lowlvl_parts[1];
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partition_info[3].mtdp = &lowlvl_parts[3];
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add_mtd_partitions(mymtd, partition_info, NUM_PARTITIONS);
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/*
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** now create a virtual MTD device by concatenating the for partitions
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** (in the sequence given by the lowlvl_parts[] array.
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*/
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merged_mtd = mtd_concat_create(lowlvl_parts, NUM_PARTITIONS, "(A)DNP Flash Concatenated");
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if(merged_mtd)
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{ /*
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** now partition the new device the way we want it. This time,
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** we do not supply mtd pointers in higlvl_partition_info, so
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** add_mtd_partitions() will register the devices.
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*/
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add_mtd_partitions(merged_mtd, higlvl_partition_info, NUM_HIGHLVL_PARTITIONS);
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}
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return 0;
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}
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static void __exit cleanup_dnpc(void)
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{
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if(merged_mtd) {
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del_mtd_partitions(merged_mtd);
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mtd_concat_destroy(merged_mtd);
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}
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if (mymtd) {
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del_mtd_partitions(mymtd);
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map_destroy(mymtd);
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}
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if (dnpc_map.virt) {
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iounmap(dnpc_map.virt);
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dnpc_unmap_flash();
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dnpc_map.virt = NULL;
|
|
}
|
|
}
|
|
|
|
module_init(init_dnpc);
|
|
module_exit(cleanup_dnpc);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
|
|
MODULE_DESCRIPTION("MTD map driver for SSV DIL/NetPC DNP & ADNP");
|