![Arnd Bergmann](/assets/img/avatar_default.png)
MMIO registers are __iomem tokens in virtual address space, not integers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
602 lines
17 KiB
C
602 lines
17 KiB
C
/*
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* drivers/media/video/omap24xxcam-dma.c
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*
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* Copyright (C) 2004 MontaVista Software, Inc.
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* Copyright (C) 2004 Texas Instruments.
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* Copyright (C) 2007 Nokia Corporation.
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*
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* Contact: Sakari Ailus <sakari.ailus@nokia.com>
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*
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* Based on code from Andy Lowe <source@mvista.com> and
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* David Cohen <david.cohen@indt.org.br>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/scatterlist.h>
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#include "omap24xxcam.h"
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/*
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*
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* DMA hardware.
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*
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*/
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/* Ack all interrupt on CSR and IRQSTATUS_L0 */
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static void omap24xxcam_dmahw_ack_all(void __iomem *base)
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{
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u32 csr;
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int i;
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for (i = 0; i < NUM_CAMDMA_CHANNELS; ++i) {
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csr = omap24xxcam_reg_in(base, CAMDMA_CSR(i));
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/* ack interrupt in CSR */
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omap24xxcam_reg_out(base, CAMDMA_CSR(i), csr);
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}
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omap24xxcam_reg_out(base, CAMDMA_IRQSTATUS_L0, 0xf);
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}
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/* Ack dmach on CSR and IRQSTATUS_L0 */
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static u32 omap24xxcam_dmahw_ack_ch(void __iomem *base, int dmach)
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{
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u32 csr;
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csr = omap24xxcam_reg_in(base, CAMDMA_CSR(dmach));
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/* ack interrupt in CSR */
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omap24xxcam_reg_out(base, CAMDMA_CSR(dmach), csr);
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/* ack interrupt in IRQSTATUS */
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omap24xxcam_reg_out(base, CAMDMA_IRQSTATUS_L0, (1 << dmach));
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return csr;
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}
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static int omap24xxcam_dmahw_running(void __iomem *base, int dmach)
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{
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return omap24xxcam_reg_in(base, CAMDMA_CCR(dmach)) & CAMDMA_CCR_ENABLE;
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}
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static void omap24xxcam_dmahw_transfer_setup(void __iomem *base, int dmach,
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dma_addr_t start, u32 len)
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{
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omap24xxcam_reg_out(base, CAMDMA_CCR(dmach),
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CAMDMA_CCR_SEL_SRC_DST_SYNC
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| CAMDMA_CCR_BS
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| CAMDMA_CCR_DST_AMODE_POST_INC
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| CAMDMA_CCR_SRC_AMODE_POST_INC
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| CAMDMA_CCR_FS
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| CAMDMA_CCR_WR_ACTIVE
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| CAMDMA_CCR_RD_ACTIVE
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| CAMDMA_CCR_SYNCHRO_CAMERA);
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omap24xxcam_reg_out(base, CAMDMA_CLNK_CTRL(dmach), 0);
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omap24xxcam_reg_out(base, CAMDMA_CEN(dmach), len);
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omap24xxcam_reg_out(base, CAMDMA_CFN(dmach), 1);
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omap24xxcam_reg_out(base, CAMDMA_CSDP(dmach),
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CAMDMA_CSDP_WRITE_MODE_POSTED
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| CAMDMA_CSDP_DST_BURST_EN_32
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| CAMDMA_CSDP_DST_PACKED
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| CAMDMA_CSDP_SRC_BURST_EN_32
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| CAMDMA_CSDP_SRC_PACKED
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| CAMDMA_CSDP_DATA_TYPE_8BITS);
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omap24xxcam_reg_out(base, CAMDMA_CSSA(dmach), 0);
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omap24xxcam_reg_out(base, CAMDMA_CDSA(dmach), start);
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omap24xxcam_reg_out(base, CAMDMA_CSEI(dmach), 0);
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omap24xxcam_reg_out(base, CAMDMA_CSFI(dmach), DMA_THRESHOLD);
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omap24xxcam_reg_out(base, CAMDMA_CDEI(dmach), 0);
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omap24xxcam_reg_out(base, CAMDMA_CDFI(dmach), 0);
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omap24xxcam_reg_out(base, CAMDMA_CSR(dmach),
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CAMDMA_CSR_MISALIGNED_ERR
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| CAMDMA_CSR_SECURE_ERR
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| CAMDMA_CSR_TRANS_ERR
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| CAMDMA_CSR_BLOCK
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| CAMDMA_CSR_DROP);
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omap24xxcam_reg_out(base, CAMDMA_CICR(dmach),
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CAMDMA_CICR_MISALIGNED_ERR_IE
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| CAMDMA_CICR_SECURE_ERR_IE
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| CAMDMA_CICR_TRANS_ERR_IE
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| CAMDMA_CICR_BLOCK_IE
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| CAMDMA_CICR_DROP_IE);
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}
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static void omap24xxcam_dmahw_transfer_start(void __iomem *base, int dmach)
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{
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omap24xxcam_reg_out(base, CAMDMA_CCR(dmach),
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CAMDMA_CCR_SEL_SRC_DST_SYNC
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| CAMDMA_CCR_BS
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| CAMDMA_CCR_DST_AMODE_POST_INC
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| CAMDMA_CCR_SRC_AMODE_POST_INC
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| CAMDMA_CCR_ENABLE
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| CAMDMA_CCR_FS
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| CAMDMA_CCR_SYNCHRO_CAMERA);
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}
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static void omap24xxcam_dmahw_transfer_chain(void __iomem *base, int dmach,
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int free_dmach)
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{
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int prev_dmach, ch;
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if (dmach == 0)
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prev_dmach = NUM_CAMDMA_CHANNELS - 1;
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else
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prev_dmach = dmach - 1;
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omap24xxcam_reg_out(base, CAMDMA_CLNK_CTRL(prev_dmach),
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CAMDMA_CLNK_CTRL_ENABLE_LNK | dmach);
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/* Did we chain the DMA transfer before the previous one
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* finished?
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*/
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ch = (dmach + free_dmach) % NUM_CAMDMA_CHANNELS;
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while (!(omap24xxcam_reg_in(base, CAMDMA_CCR(ch))
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& CAMDMA_CCR_ENABLE)) {
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if (ch == dmach) {
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/* The previous transfer has ended and this one
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* hasn't started, so we must not have chained
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* to the previous one in time. We'll have to
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* start it now.
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*/
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omap24xxcam_dmahw_transfer_start(base, dmach);
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break;
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} else
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ch = (ch + 1) % NUM_CAMDMA_CHANNELS;
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}
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}
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/* Abort all chained DMA transfers. After all transfers have been
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* aborted and the DMA controller is idle, the completion routines for
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* any aborted transfers will be called in sequence. The DMA
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* controller may not be idle after this routine completes, because
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* the completion routines might start new transfers.
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*/
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static void omap24xxcam_dmahw_abort_ch(void __iomem *base, int dmach)
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{
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/* mask all interrupts from this channel */
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omap24xxcam_reg_out(base, CAMDMA_CICR(dmach), 0);
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/* unlink this channel */
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omap24xxcam_reg_merge(base, CAMDMA_CLNK_CTRL(dmach), 0,
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CAMDMA_CLNK_CTRL_ENABLE_LNK);
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/* disable this channel */
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omap24xxcam_reg_merge(base, CAMDMA_CCR(dmach), 0, CAMDMA_CCR_ENABLE);
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}
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static void omap24xxcam_dmahw_init(void __iomem *base)
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{
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omap24xxcam_reg_out(base, CAMDMA_OCP_SYSCONFIG,
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CAMDMA_OCP_SYSCONFIG_MIDLEMODE_FSTANDBY
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| CAMDMA_OCP_SYSCONFIG_SIDLEMODE_FIDLE
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| CAMDMA_OCP_SYSCONFIG_AUTOIDLE);
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omap24xxcam_reg_merge(base, CAMDMA_GCR, 0x10,
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CAMDMA_GCR_MAX_CHANNEL_FIFO_DEPTH);
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omap24xxcam_reg_out(base, CAMDMA_IRQENABLE_L0, 0xf);
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}
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/*
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*
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* Individual DMA channel handling.
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*
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*/
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/* Start a DMA transfer from the camera to memory.
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* Returns zero if the transfer was successfully started, or non-zero if all
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* DMA channels are already in use or starting is currently inhibited.
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*/
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static int omap24xxcam_dma_start(struct omap24xxcam_dma *dma, dma_addr_t start,
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u32 len, dma_callback_t callback, void *arg)
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{
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unsigned long flags;
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int dmach;
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spin_lock_irqsave(&dma->lock, flags);
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if (!dma->free_dmach || atomic_read(&dma->dma_stop)) {
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spin_unlock_irqrestore(&dma->lock, flags);
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return -EBUSY;
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}
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dmach = dma->next_dmach;
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dma->ch_state[dmach].callback = callback;
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dma->ch_state[dmach].arg = arg;
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omap24xxcam_dmahw_transfer_setup(dma->base, dmach, start, len);
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/* We're ready to start the DMA transfer. */
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if (dma->free_dmach < NUM_CAMDMA_CHANNELS) {
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/* A transfer is already in progress, so try to chain to it. */
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omap24xxcam_dmahw_transfer_chain(dma->base, dmach,
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dma->free_dmach);
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} else {
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/* No transfer is in progress, so we'll just start this one
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* now.
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*/
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omap24xxcam_dmahw_transfer_start(dma->base, dmach);
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}
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dma->next_dmach = (dma->next_dmach + 1) % NUM_CAMDMA_CHANNELS;
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dma->free_dmach--;
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spin_unlock_irqrestore(&dma->lock, flags);
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return 0;
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}
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/* Abort all chained DMA transfers. After all transfers have been
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* aborted and the DMA controller is idle, the completion routines for
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* any aborted transfers will be called in sequence. The DMA
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* controller may not be idle after this routine completes, because
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* the completion routines might start new transfers.
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*/
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static void omap24xxcam_dma_abort(struct omap24xxcam_dma *dma, u32 csr)
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{
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unsigned long flags;
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int dmach, i, free_dmach;
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dma_callback_t callback;
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void *arg;
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spin_lock_irqsave(&dma->lock, flags);
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/* stop any DMA transfers in progress */
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dmach = (dma->next_dmach + dma->free_dmach) % NUM_CAMDMA_CHANNELS;
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for (i = 0; i < NUM_CAMDMA_CHANNELS; i++) {
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omap24xxcam_dmahw_abort_ch(dma->base, dmach);
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dmach = (dmach + 1) % NUM_CAMDMA_CHANNELS;
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}
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/* We have to be careful here because the callback routine
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* might start a new DMA transfer, and we only want to abort
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* transfers that were started before this routine was called.
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*/
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free_dmach = dma->free_dmach;
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while ((dma->free_dmach < NUM_CAMDMA_CHANNELS) &&
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(free_dmach < NUM_CAMDMA_CHANNELS)) {
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dmach = (dma->next_dmach + dma->free_dmach)
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% NUM_CAMDMA_CHANNELS;
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callback = dma->ch_state[dmach].callback;
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arg = dma->ch_state[dmach].arg;
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dma->free_dmach++;
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free_dmach++;
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if (callback) {
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/* leave interrupts disabled during callback */
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spin_unlock(&dma->lock);
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(*callback) (dma, csr, arg);
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spin_lock(&dma->lock);
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}
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}
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spin_unlock_irqrestore(&dma->lock, flags);
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}
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/* Abort all chained DMA transfers. After all transfers have been
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* aborted and the DMA controller is idle, the completion routines for
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* any aborted transfers will be called in sequence. If the completion
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* routines attempt to start a new DMA transfer it will fail, so the
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* DMA controller will be idle after this routine completes.
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*/
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static void omap24xxcam_dma_stop(struct omap24xxcam_dma *dma, u32 csr)
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{
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atomic_inc(&dma->dma_stop);
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omap24xxcam_dma_abort(dma, csr);
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atomic_dec(&dma->dma_stop);
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}
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/* Camera DMA interrupt service routine. */
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void omap24xxcam_dma_isr(struct omap24xxcam_dma *dma)
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{
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int dmach;
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dma_callback_t callback;
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void *arg;
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u32 csr;
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const u32 csr_error = CAMDMA_CSR_MISALIGNED_ERR
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| CAMDMA_CSR_SUPERVISOR_ERR | CAMDMA_CSR_SECURE_ERR
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| CAMDMA_CSR_TRANS_ERR | CAMDMA_CSR_DROP;
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spin_lock(&dma->lock);
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if (dma->free_dmach == NUM_CAMDMA_CHANNELS) {
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/* A camera DMA interrupt occurred while all channels
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* are idle, so we'll acknowledge the interrupt in the
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* IRQSTATUS register and exit.
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*/
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omap24xxcam_dmahw_ack_all(dma->base);
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spin_unlock(&dma->lock);
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return;
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}
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while (dma->free_dmach < NUM_CAMDMA_CHANNELS) {
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dmach = (dma->next_dmach + dma->free_dmach)
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% NUM_CAMDMA_CHANNELS;
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if (omap24xxcam_dmahw_running(dma->base, dmach)) {
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/* This buffer hasn't finished yet, so we're done. */
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break;
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}
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csr = omap24xxcam_dmahw_ack_ch(dma->base, dmach);
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if (csr & csr_error) {
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/* A DMA error occurred, so stop all DMA
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* transfers in progress.
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*/
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spin_unlock(&dma->lock);
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omap24xxcam_dma_stop(dma, csr);
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return;
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} else {
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callback = dma->ch_state[dmach].callback;
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arg = dma->ch_state[dmach].arg;
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dma->free_dmach++;
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if (callback) {
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spin_unlock(&dma->lock);
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(*callback) (dma, csr, arg);
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spin_lock(&dma->lock);
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}
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}
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}
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spin_unlock(&dma->lock);
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omap24xxcam_sgdma_process(
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container_of(dma, struct omap24xxcam_sgdma, dma));
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}
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void omap24xxcam_dma_hwinit(struct omap24xxcam_dma *dma)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma->lock, flags);
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omap24xxcam_dmahw_init(dma->base);
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spin_unlock_irqrestore(&dma->lock, flags);
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}
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static void omap24xxcam_dma_init(struct omap24xxcam_dma *dma,
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void __iomem *base)
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{
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int ch;
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/* group all channels on DMA IRQ0 and unmask irq */
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spin_lock_init(&dma->lock);
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dma->base = base;
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dma->free_dmach = NUM_CAMDMA_CHANNELS;
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dma->next_dmach = 0;
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for (ch = 0; ch < NUM_CAMDMA_CHANNELS; ch++) {
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dma->ch_state[ch].callback = NULL;
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dma->ch_state[ch].arg = NULL;
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}
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}
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/*
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*
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* Scatter-gather DMA.
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*
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* High-level DMA construct for transferring whole picture frames to
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* memory that is discontinuous.
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*
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*/
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/* DMA completion routine for the scatter-gather DMA fragments. */
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static void omap24xxcam_sgdma_callback(struct omap24xxcam_dma *dma, u32 csr,
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void *arg)
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{
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struct omap24xxcam_sgdma *sgdma =
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container_of(dma, struct omap24xxcam_sgdma, dma);
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int sgslot = (int)arg;
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struct sgdma_state *sg_state;
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const u32 csr_error = CAMDMA_CSR_MISALIGNED_ERR
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| CAMDMA_CSR_SUPERVISOR_ERR | CAMDMA_CSR_SECURE_ERR
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| CAMDMA_CSR_TRANS_ERR | CAMDMA_CSR_DROP;
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spin_lock(&sgdma->lock);
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/* We got an interrupt, we can remove the timer */
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del_timer(&sgdma->reset_timer);
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sg_state = sgdma->sg_state + sgslot;
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if (!sg_state->queued_sglist) {
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spin_unlock(&sgdma->lock);
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printk(KERN_ERR "%s: sgdma completed when none queued!\n",
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__func__);
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return;
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}
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sg_state->csr |= csr;
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if (!--sg_state->queued_sglist) {
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/* Queue for this sglist is empty, so check to see if we're
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* done.
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*/
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if ((sg_state->next_sglist == sg_state->sglen)
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|| (sg_state->csr & csr_error)) {
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sgdma_callback_t callback = sg_state->callback;
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void *arg = sg_state->arg;
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u32 sg_csr = sg_state->csr;
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/* All done with this sglist */
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sgdma->free_sgdma++;
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if (callback) {
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spin_unlock(&sgdma->lock);
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(*callback) (sgdma, sg_csr, arg);
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return;
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}
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}
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}
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spin_unlock(&sgdma->lock);
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}
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/* Start queued scatter-gather DMA transfers. */
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void omap24xxcam_sgdma_process(struct omap24xxcam_sgdma *sgdma)
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{
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unsigned long flags;
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int queued_sgdma, sgslot;
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struct sgdma_state *sg_state;
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const u32 csr_error = CAMDMA_CSR_MISALIGNED_ERR
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| CAMDMA_CSR_SUPERVISOR_ERR | CAMDMA_CSR_SECURE_ERR
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| CAMDMA_CSR_TRANS_ERR | CAMDMA_CSR_DROP;
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spin_lock_irqsave(&sgdma->lock, flags);
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queued_sgdma = NUM_SG_DMA - sgdma->free_sgdma;
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sgslot = (sgdma->next_sgdma + sgdma->free_sgdma) % NUM_SG_DMA;
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while (queued_sgdma > 0) {
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sg_state = sgdma->sg_state + sgslot;
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while ((sg_state->next_sglist < sg_state->sglen) &&
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!(sg_state->csr & csr_error)) {
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const struct scatterlist *sglist;
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unsigned int len;
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sglist = sg_state->sglist + sg_state->next_sglist;
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/* try to start the next DMA transfer */
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if (sg_state->next_sglist + 1 == sg_state->sglen) {
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/*
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* On the last sg, we handle the case where
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* cam->img.pix.sizeimage % PAGE_ALIGN != 0
|
|
*/
|
|
len = sg_state->len - sg_state->bytes_read;
|
|
} else {
|
|
len = sg_dma_len(sglist);
|
|
}
|
|
|
|
if (omap24xxcam_dma_start(&sgdma->dma,
|
|
sg_dma_address(sglist),
|
|
len,
|
|
omap24xxcam_sgdma_callback,
|
|
(void *)sgslot)) {
|
|
/* DMA start failed */
|
|
spin_unlock_irqrestore(&sgdma->lock, flags);
|
|
return;
|
|
} else {
|
|
unsigned long expires;
|
|
/* DMA start was successful */
|
|
sg_state->next_sglist++;
|
|
sg_state->bytes_read += len;
|
|
sg_state->queued_sglist++;
|
|
|
|
/* We start the reset timer */
|
|
expires = jiffies + HZ;
|
|
mod_timer(&sgdma->reset_timer, expires);
|
|
}
|
|
}
|
|
queued_sgdma--;
|
|
sgslot = (sgslot + 1) % NUM_SG_DMA;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&sgdma->lock, flags);
|
|
}
|
|
|
|
/*
|
|
* Queue a scatter-gather DMA transfer from the camera to memory.
|
|
* Returns zero if the transfer was successfully queued, or non-zero
|
|
* if all of the scatter-gather slots are already in use.
|
|
*/
|
|
int omap24xxcam_sgdma_queue(struct omap24xxcam_sgdma *sgdma,
|
|
const struct scatterlist *sglist, int sglen,
|
|
int len, sgdma_callback_t callback, void *arg)
|
|
{
|
|
unsigned long flags;
|
|
struct sgdma_state *sg_state;
|
|
|
|
if ((sglen < 0) || ((sglen > 0) && !sglist))
|
|
return -EINVAL;
|
|
|
|
spin_lock_irqsave(&sgdma->lock, flags);
|
|
|
|
if (!sgdma->free_sgdma) {
|
|
spin_unlock_irqrestore(&sgdma->lock, flags);
|
|
return -EBUSY;
|
|
}
|
|
|
|
sg_state = sgdma->sg_state + sgdma->next_sgdma;
|
|
|
|
sg_state->sglist = sglist;
|
|
sg_state->sglen = sglen;
|
|
sg_state->next_sglist = 0;
|
|
sg_state->bytes_read = 0;
|
|
sg_state->len = len;
|
|
sg_state->queued_sglist = 0;
|
|
sg_state->csr = 0;
|
|
sg_state->callback = callback;
|
|
sg_state->arg = arg;
|
|
|
|
sgdma->next_sgdma = (sgdma->next_sgdma + 1) % NUM_SG_DMA;
|
|
sgdma->free_sgdma--;
|
|
|
|
spin_unlock_irqrestore(&sgdma->lock, flags);
|
|
|
|
omap24xxcam_sgdma_process(sgdma);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Sync scatter-gather DMA by aborting any DMA transfers currently in progress.
|
|
* Any queued scatter-gather DMA transactions that have not yet been started
|
|
* will remain queued. The DMA controller will be idle after this routine
|
|
* completes. When the scatter-gather queue is restarted, the next
|
|
* scatter-gather DMA transfer will begin at the start of a new transaction.
|
|
*/
|
|
void omap24xxcam_sgdma_sync(struct omap24xxcam_sgdma *sgdma)
|
|
{
|
|
unsigned long flags;
|
|
int sgslot;
|
|
struct sgdma_state *sg_state;
|
|
u32 csr = CAMDMA_CSR_TRANS_ERR;
|
|
|
|
/* stop any DMA transfers in progress */
|
|
omap24xxcam_dma_stop(&sgdma->dma, csr);
|
|
|
|
spin_lock_irqsave(&sgdma->lock, flags);
|
|
|
|
if (sgdma->free_sgdma < NUM_SG_DMA) {
|
|
sgslot = (sgdma->next_sgdma + sgdma->free_sgdma) % NUM_SG_DMA;
|
|
sg_state = sgdma->sg_state + sgslot;
|
|
if (sg_state->next_sglist != 0) {
|
|
/* This DMA transfer was in progress, so abort it. */
|
|
sgdma_callback_t callback = sg_state->callback;
|
|
void *arg = sg_state->arg;
|
|
sgdma->free_sgdma++;
|
|
if (callback) {
|
|
/* leave interrupts masked */
|
|
spin_unlock(&sgdma->lock);
|
|
(*callback) (sgdma, csr, arg);
|
|
spin_lock(&sgdma->lock);
|
|
}
|
|
}
|
|
}
|
|
|
|
spin_unlock_irqrestore(&sgdma->lock, flags);
|
|
}
|
|
|
|
void omap24xxcam_sgdma_init(struct omap24xxcam_sgdma *sgdma,
|
|
void __iomem *base,
|
|
void (*reset_callback)(unsigned long data),
|
|
unsigned long reset_callback_data)
|
|
{
|
|
int sg;
|
|
|
|
spin_lock_init(&sgdma->lock);
|
|
sgdma->free_sgdma = NUM_SG_DMA;
|
|
sgdma->next_sgdma = 0;
|
|
for (sg = 0; sg < NUM_SG_DMA; sg++) {
|
|
sgdma->sg_state[sg].sglen = 0;
|
|
sgdma->sg_state[sg].next_sglist = 0;
|
|
sgdma->sg_state[sg].bytes_read = 0;
|
|
sgdma->sg_state[sg].queued_sglist = 0;
|
|
sgdma->sg_state[sg].csr = 0;
|
|
sgdma->sg_state[sg].callback = NULL;
|
|
sgdma->sg_state[sg].arg = NULL;
|
|
}
|
|
|
|
omap24xxcam_dma_init(&sgdma->dma, base);
|
|
setup_timer(&sgdma->reset_timer, reset_callback, reset_callback_data);
|
|
}
|