4334ac2db2
The SAMA5 and SAM9x5 series both have drive strength options for the PIOs. This patch adds the ability to set one of three hardware options for drive strengths of low, medium or high for the each pin. The actual current output of the chip based on the setting is defined in the datasheets and varies per pins separate from banks and with supply voltage. This patch adds three new dt-bindings that allow setting the strength when configuring pins. By default, no change will be made to the drive strength of a pin from its reset value. Due to the difference between the register addresses of the SAMA5 and SAM9x5 series, a new sama5d3-pinctrl id was added. Signed-off-by: Marek Roszko <mark.roszko@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/*
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* This header provides constants for most at91 pinctrl bindings.
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*
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* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* GPLv2 only
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*/
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#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
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#define __DT_BINDINGS_AT91_PINCTRL_H__
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#define AT91_PINCTRL_NONE (0 << 0)
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#define AT91_PINCTRL_PULL_UP (1 << 0)
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#define AT91_PINCTRL_MULTI_DRIVE (1 << 1)
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#define AT91_PINCTRL_DEGLITCH (1 << 2)
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#define AT91_PINCTRL_PULL_DOWN (1 << 3)
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#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
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#define AT91_PINCTRL_DEBOUNCE (1 << 16)
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#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
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#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
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#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
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#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
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#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
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#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
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#define AT91_PIOA 0
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#define AT91_PIOB 1
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#define AT91_PIOC 2
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#define AT91_PIOD 3
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#define AT91_PIOE 4
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#define AT91_PERIPH_GPIO 0
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#define AT91_PERIPH_A 1
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#define AT91_PERIPH_B 2
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#define AT91_PERIPH_C 3
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#define AT91_PERIPH_D 4
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#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */
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