155a97a3d7
KVM's existing shadow MMU code already supports nested TDP. To use it, we need to set up a new "MMU context" for nested EPT, and create a few callbacks for it (nested_ept_*()). This context should also use the EPT versions of the page table access functions (defined in the previous patch). Then, we need to switch back and forth between this nested context and the regular MMU context when switching between L1 and L2 (when L1 runs this L2 with EPT). Reviewed-by: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com> Signed-off-by: Nadav Har'El <nyh@il.ibm.com> Signed-off-by: Jun Nakajima <jun.nakajima@intel.com> Signed-off-by: Xinhao Xu <xinhao.xu@intel.com> Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
#ifndef __KVM_X86_MMU_H
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#define __KVM_X86_MMU_H
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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#define PT64_PT_BITS 9
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#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
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#define PT32_PT_BITS 10
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#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
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#define PT_WRITABLE_SHIFT 1
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#define PT_PRESENT_MASK (1ULL << 0)
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#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
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#define PT_USER_MASK (1ULL << 2)
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#define PT_PWT_MASK (1ULL << 3)
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#define PT_PCD_MASK (1ULL << 4)
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#define PT_ACCESSED_SHIFT 5
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#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
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#define PT_DIRTY_SHIFT 6
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#define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
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#define PT_PAGE_SIZE_SHIFT 7
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#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
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#define PT_PAT_MASK (1ULL << 7)
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#define PT_GLOBAL_MASK (1ULL << 8)
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#define PT64_NX_SHIFT 63
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#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
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#define PT_PAT_SHIFT 7
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#define PT_DIR_PAT_SHIFT 12
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#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
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#define PT32_DIR_PSE36_SIZE 4
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#define PT32_DIR_PSE36_SHIFT 13
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#define PT32_DIR_PSE36_MASK \
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(((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
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#define PT64_ROOT_LEVEL 4
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#define PT32_ROOT_LEVEL 2
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#define PT32E_ROOT_LEVEL 3
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#define PT_PDPE_LEVEL 3
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#define PT_DIRECTORY_LEVEL 2
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#define PT_PAGE_TABLE_LEVEL 1
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#define PFERR_PRESENT_MASK (1U << 0)
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#define PFERR_WRITE_MASK (1U << 1)
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#define PFERR_USER_MASK (1U << 2)
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#define PFERR_RSVD_MASK (1U << 3)
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#define PFERR_FETCH_MASK (1U << 4)
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int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]);
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void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask);
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/*
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* Return values of handle_mmio_page_fault_common:
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* RET_MMIO_PF_EMULATE: it is a real mmio page fault, emulate the instruction
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* directly.
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* RET_MMIO_PF_INVALID: invalid spte is detected then let the real page
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* fault path update the mmio spte.
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* RET_MMIO_PF_RETRY: let CPU fault again on the address.
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* RET_MMIO_PF_BUG: bug is detected.
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*/
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enum {
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RET_MMIO_PF_EMULATE = 1,
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RET_MMIO_PF_INVALID = 2,
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RET_MMIO_PF_RETRY = 0,
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RET_MMIO_PF_BUG = -1
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};
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int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct);
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int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
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int kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
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bool execonly);
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static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
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{
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if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
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return kvm->arch.n_max_mmu_pages -
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kvm->arch.n_used_mmu_pages;
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return 0;
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}
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static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
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{
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if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
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return 0;
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return kvm_mmu_load(vcpu);
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}
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static inline int is_present_gpte(unsigned long pte)
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{
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return pte & PT_PRESENT_MASK;
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}
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static inline int is_writable_pte(unsigned long pte)
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{
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return pte & PT_WRITABLE_MASK;
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}
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static inline bool is_write_protection(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
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}
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/*
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* Will a fault with a given page-fault error code (pfec) cause a permission
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* fault with the given access (in ACC_* format)?
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*/
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static inline bool permission_fault(struct kvm_mmu *mmu, unsigned pte_access,
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unsigned pfec)
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{
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return (mmu->permissions[pfec >> 1] >> pte_access) & 1;
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}
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void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm);
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#endif
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