739 lines
17 KiB
C
739 lines
17 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <video/dpu.h>
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#include "dpu-prv.h"
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#define FD_NUM_V1 4
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#define FD_NUM_V2 2
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static const u32 fd_vproc_cap_v1[FD_NUM_V1] = {
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DPU_VPROC_CAP_HSCALER4 | DPU_VPROC_CAP_VSCALER4 |
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DPU_VPROC_CAP_FETCHECO0,
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DPU_VPROC_CAP_HSCALER5 | DPU_VPROC_CAP_VSCALER5 |
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DPU_VPROC_CAP_FETCHECO1,
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DPU_VPROC_CAP_HSCALER4 | DPU_VPROC_CAP_VSCALER4 |
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DPU_VPROC_CAP_FETCHECO0,
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DPU_VPROC_CAP_HSCALER5 | DPU_VPROC_CAP_VSCALER5 |
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DPU_VPROC_CAP_FETCHECO1,
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};
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static const u32 fd_vproc_cap_v2[FD_NUM_V2] = {
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DPU_VPROC_CAP_HSCALER4 | DPU_VPROC_CAP_VSCALER4 |
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DPU_VPROC_CAP_FETCHECO0,
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DPU_VPROC_CAP_HSCALER5 | DPU_VPROC_CAP_VSCALER5 |
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DPU_VPROC_CAP_FETCHECO1,
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};
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#define PIXENGCFG_DYNAMIC 0x8
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#define SRC_NUM_V1 3
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#define SRC_NUM_V2 4
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static const fd_dynamic_src_sel_t fd_srcs_v1[FD_NUM_V1][SRC_NUM_V1] = {
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{ FD_SRC_DISABLE, FD_SRC_FETCHECO0, FD_SRC_FETCHDECODE2 },
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{ FD_SRC_DISABLE, FD_SRC_FETCHECO1, FD_SRC_FETCHDECODE3 },
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{ FD_SRC_DISABLE, FD_SRC_FETCHECO0, FD_SRC_FETCHECO2 },
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{ FD_SRC_DISABLE, FD_SRC_FETCHECO1, FD_SRC_FETCHECO2 },
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};
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static const fd_dynamic_src_sel_t fd_srcs_v2[FD_NUM_V2][SRC_NUM_V2] = {
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{
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FD_SRC_DISABLE, FD_SRC_FETCHECO0,
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FD_SRC_FETCHDECODE1, FD_SRC_FETCHWARP2
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}, {
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FD_SRC_DISABLE, FD_SRC_FETCHECO1,
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FD_SRC_FETCHDECODE0, FD_SRC_FETCHWARP2
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},
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};
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#define PIXENGCFG_STATUS 0xC
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#define RINGBUFSTARTADDR0 0x10
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#define RINGBUFWRAPADDR0 0x14
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#define FRAMEPROPERTIES0 0x18
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#define BASEADDRESS0 0x1C
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#define SOURCEBUFFERATTRIBUTES0 0x20
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#define SOURCEBUFFERDIMENSION0 0x24
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#define COLORCOMPONENTBITS0 0x28
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#define COLORCOMPONENTSHIFT0 0x2C
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#define LAYEROFFSET0 0x30
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#define CLIPWINDOWOFFSET0 0x34
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#define CLIPWINDOWDIMENSIONS0 0x38
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#define CONSTANTCOLOR0 0x3C
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#define LAYERPROPERTY0 0x40
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#define FRAMEDIMENSIONS 0x44
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#define FRAMERESAMPLING 0x48
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#define DECODECONTROL 0x4C
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#define SOURCEBUFFERLENGTH 0x50
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#define CONTROL 0x54
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#define CONTROLTRIGGER 0x58
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#define START 0x5C
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#define FETCHTYPE 0x60
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#define DECODERSTATUS 0x64
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#define READADDRESS0 0x68
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#define BURSTBUFFERPROPERTIES 0x6C
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#define STATUS 0x70
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#define HIDDENSTATUS 0x74
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static const shadow_load_req_t fd_shdlreqs[] = {
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SHLDREQID_FETCHDECODE0, SHLDREQID_FETCHDECODE1,
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SHLDREQID_FETCHDECODE2, SHLDREQID_FETCHDECODE3,
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};
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struct dpu_fetchdecode {
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struct dpu_fetchunit fu;
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fetchtype_t fetchtype;
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shadow_load_req_t shdlreq;
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};
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int fetchdecode_pixengcfg_dynamic_src_sel(struct dpu_fetchunit *fu,
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fd_dynamic_src_sel_t src)
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{
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struct dpu_soc *dpu = fu->dpu;
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const struct dpu_devtype *devtype = dpu->devtype;
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int i;
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mutex_lock(&fu->mutex);
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if (devtype->version == DPU_V1) {
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for (i = 0; i < SRC_NUM_V1; i++) {
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if (fd_srcs_v1[fu->id][i] == src) {
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dpu_pec_fu_write(fu, src, PIXENGCFG_DYNAMIC);
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mutex_unlock(&fu->mutex);
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return 0;
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}
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}
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} else if (devtype->version == DPU_V2) {
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const unsigned int *block_id_map = devtype->sw2hw_block_id_map;
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u32 mapped_src;
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if (WARN_ON(!block_id_map))
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return -EINVAL;
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for (i = 0; i < SRC_NUM_V2; i++) {
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if (fd_srcs_v2[fu->id][i] == src) {
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mapped_src = block_id_map[src];
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if (WARN_ON(mapped_src == NA))
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return -EINVAL;
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dpu_pec_fu_write(fu, mapped_src,
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PIXENGCFG_DYNAMIC);
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mutex_unlock(&fu->mutex);
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return 0;
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}
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}
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} else {
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WARN_ON(1);
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}
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mutex_unlock(&fu->mutex);
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(fetchdecode_pixengcfg_dynamic_src_sel);
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static void
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fetchdecode_set_baseaddress(struct dpu_fetchunit *fu, dma_addr_t paddr)
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{
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, paddr, BASEADDRESS0);
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mutex_unlock(&fu->mutex);
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}
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static void fetchdecode_set_src_bpp(struct dpu_fetchunit *fu, int bpp)
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{
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u32 val;
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mutex_lock(&fu->mutex);
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val = dpu_fu_read(fu, SOURCEBUFFERATTRIBUTES0);
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val &= ~0x3f0000;
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val |= BITSPERPIXEL(bpp);
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dpu_fu_write(fu, val, SOURCEBUFFERATTRIBUTES0);
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mutex_unlock(&fu->mutex);
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}
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static void
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fetchdecode_set_src_stride(struct dpu_fetchunit *fu,
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unsigned int width, int bpp, unsigned int stride,
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dma_addr_t baddr, bool use_prefetch)
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{
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unsigned int burst_size;
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u32 val;
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if (use_prefetch) {
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/*
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* address TKT343664:
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* fetch unit base address has to align to burst size
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*/
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burst_size = 1 << (ffs(baddr) - 1);
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burst_size = min(burst_size, 128U);
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stride = width * (bpp >> 3);
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/*
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* address TKT339017:
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* fixup for burst size vs stride mismatch
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*/
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stride = round_up(stride, burst_size);
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}
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mutex_lock(&fu->mutex);
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val = dpu_fu_read(fu, SOURCEBUFFERATTRIBUTES0);
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val &= ~0xffff;
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val |= STRIDE(stride);
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dpu_fu_write(fu, val, SOURCEBUFFERATTRIBUTES0);
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mutex_unlock(&fu->mutex);
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}
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static void
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fetchdecode_set_src_buf_dimensions(struct dpu_fetchunit *fu,
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unsigned int w, unsigned int h,
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u32 unused, bool deinterlace)
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{
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u32 val;
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if (deinterlace)
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h /= 2;
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val = LINEWIDTH(w) | LINECOUNT(h);
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, val, SOURCEBUFFERDIMENSION0);
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mutex_unlock(&fu->mutex);
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}
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static void
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fetchdecode_set_fmt(struct dpu_fetchunit *fu, u32 fmt, bool deinterlace)
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{
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u32 val, bits, shift;
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bool is_planar_yuv = false, is_rastermode_yuv422 = false;
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bool is_yuv422upsamplingmode_interpolate = false;
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bool is_inputselect_compact = false;
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bool need_csc = false;
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int i;
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switch (fmt) {
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_UYVY:
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is_rastermode_yuv422 = true;
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is_yuv422upsamplingmode_interpolate = true;
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need_csc = true;
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break;
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case DRM_FORMAT_NV16:
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case DRM_FORMAT_NV61:
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is_yuv422upsamplingmode_interpolate = true;
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/* fall-through */
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_NV21:
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if (deinterlace)
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is_yuv422upsamplingmode_interpolate = true;
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is_planar_yuv = true;
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is_rastermode_yuv422 = true;
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is_inputselect_compact = true;
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need_csc = true;
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break;
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case DRM_FORMAT_NV24:
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case DRM_FORMAT_NV42:
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is_planar_yuv = true;
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is_yuv422upsamplingmode_interpolate = true;
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is_inputselect_compact = true;
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need_csc = true;
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break;
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default:
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break;
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}
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mutex_lock(&fu->mutex);
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val = dpu_fu_read(fu, CONTROL);
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val &= ~YUV422UPSAMPLINGMODE_MASK;
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val &= ~INPUTSELECT_MASK;
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val &= ~RASTERMODE_MASK;
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if (is_yuv422upsamplingmode_interpolate)
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val |= YUV422UPSAMPLINGMODE(YUV422UPSAMPLINGMODE__INTERPOLATE);
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else
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val |= YUV422UPSAMPLINGMODE(YUV422UPSAMPLINGMODE__REPLICATE);
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if (is_inputselect_compact)
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val |= INPUTSELECT(INPUTSELECT__COMPPACK);
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else
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val |= INPUTSELECT(INPUTSELECT__INACTIVE);
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if (is_rastermode_yuv422)
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val |= RASTERMODE(RASTERMODE__YUV422);
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else
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val |= RASTERMODE(RASTERMODE__NORMAL);
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dpu_fu_write(fu, val, CONTROL);
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val = dpu_fu_read(fu, LAYERPROPERTY0);
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val &= ~YUVCONVERSIONMODE_MASK;
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if (need_csc)
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/*
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* assuming fetchdecode always ouputs RGB pixel formats
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*
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* FIXME:
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* determine correct standard here - ITU601 or ITU601_FR
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* or ITU709
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*/
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val |= YUVCONVERSIONMODE(YUVCONVERSIONMODE__ITU601_FR);
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else
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val |= YUVCONVERSIONMODE(YUVCONVERSIONMODE__OFF);
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dpu_fu_write(fu, val, LAYERPROPERTY0);
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mutex_unlock(&fu->mutex);
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for (i = 0; i < ARRAY_SIZE(dpu_pixel_format_matrix); i++) {
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if (dpu_pixel_format_matrix[i].pixel_format == fmt) {
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bits = dpu_pixel_format_matrix[i].bits;
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shift = dpu_pixel_format_matrix[i].shift;
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if (is_planar_yuv) {
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bits &= ~(U_BITS_MASK | V_BITS_MASK);
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shift &= ~(U_SHIFT_MASK | V_SHIFT_MASK);
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}
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, bits, COLORCOMPONENTBITS0);
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dpu_fu_write(fu, shift, COLORCOMPONENTSHIFT0);
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mutex_unlock(&fu->mutex);
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return;
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}
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}
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WARN_ON(1);
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}
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void fetchdecode_layeroffset(struct dpu_fetchunit *fu, unsigned int x,
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unsigned int y)
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{
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u32 val;
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val = LAYERXOFFSET(x) | LAYERYOFFSET(y);
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, val, LAYEROFFSET0);
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mutex_unlock(&fu->mutex);
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}
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EXPORT_SYMBOL_GPL(fetchdecode_layeroffset);
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void fetchdecode_clipoffset(struct dpu_fetchunit *fu, unsigned int x,
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unsigned int y)
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{
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u32 val;
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val = CLIPWINDOWXOFFSET(x) | CLIPWINDOWYOFFSET(y);
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, val, CLIPWINDOWOFFSET0);
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mutex_unlock(&fu->mutex);
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}
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EXPORT_SYMBOL_GPL(fetchdecode_clipoffset);
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static void fetchdecode_enable_src_buf(struct dpu_fetchunit *fu)
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{
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u32 val;
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mutex_lock(&fu->mutex);
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val = dpu_fu_read(fu, LAYERPROPERTY0);
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val |= SOURCEBUFFERENABLE;
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dpu_fu_write(fu, val, LAYERPROPERTY0);
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mutex_unlock(&fu->mutex);
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}
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static void fetchdecode_disable_src_buf(struct dpu_fetchunit *fu)
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{
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u32 val;
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mutex_lock(&fu->mutex);
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val = dpu_fu_read(fu, LAYERPROPERTY0);
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val &= ~SOURCEBUFFERENABLE;
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dpu_fu_write(fu, val, LAYERPROPERTY0);
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mutex_unlock(&fu->mutex);
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}
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static bool fetchdecode_is_enabled(struct dpu_fetchunit *fu)
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{
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u32 val;
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mutex_lock(&fu->mutex);
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val = dpu_fu_read(fu, LAYERPROPERTY0);
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mutex_unlock(&fu->mutex);
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return !!(val & SOURCEBUFFERENABLE);
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}
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void fetchdecode_clipdimensions(struct dpu_fetchunit *fu, unsigned int w,
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unsigned int h)
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{
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u32 val;
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val = CLIPWINDOWWIDTH(w) | CLIPWINDOWHEIGHT(h);
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, val, CLIPWINDOWDIMENSIONS0);
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mutex_unlock(&fu->mutex);
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}
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EXPORT_SYMBOL_GPL(fetchdecode_clipdimensions);
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static void
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fetchdecode_set_framedimensions(struct dpu_fetchunit *fu,
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unsigned int w, unsigned int h,
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bool deinterlace)
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{
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u32 val;
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if (deinterlace)
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h /= 2;
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val = FRAMEWIDTH(w) | FRAMEHEIGHT(h);
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, val, FRAMEDIMENSIONS);
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mutex_unlock(&fu->mutex);
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}
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void fetchdecode_rgb_constantcolor(struct dpu_fetchunit *fu,
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u8 r, u8 g, u8 b, u8 a)
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{
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u32 val;
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val = rgb_color(r, g, b, a);
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, val, CONSTANTCOLOR0);
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mutex_unlock(&fu->mutex);
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}
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EXPORT_SYMBOL_GPL(fetchdecode_rgb_constantcolor);
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void fetchdecode_yuv_constantcolor(struct dpu_fetchunit *fu, u8 y, u8 u, u8 v)
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{
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u32 val;
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val = yuv_color(y, u, v);
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, val, CONSTANTCOLOR0);
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mutex_unlock(&fu->mutex);
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}
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EXPORT_SYMBOL_GPL(fetchdecode_yuv_constantcolor);
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static void fetchdecode_set_controltrigger(struct dpu_fetchunit *fu)
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{
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mutex_lock(&fu->mutex);
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dpu_fu_write(fu, SHDTOKGEN, CONTROLTRIGGER);
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mutex_unlock(&fu->mutex);
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}
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int fetchdecode_fetchtype(struct dpu_fetchunit *fu, fetchtype_t *type)
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{
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struct dpu_soc *dpu = fu->dpu;
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u32 val;
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mutex_lock(&fu->mutex);
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val = dpu_fu_read(fu, FETCHTYPE);
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val &= FETCHTYPE_MASK;
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mutex_unlock(&fu->mutex);
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switch (val) {
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case FETCHTYPE__DECODE:
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dev_dbg(dpu->dev, "FetchDecode%d with RL and RLAD decoder\n",
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fu->id);
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break;
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case FETCHTYPE__LAYER:
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dev_dbg(dpu->dev, "FetchDecode%d with fractional "
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"plane(8 layers)\n", fu->id);
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break;
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case FETCHTYPE__WARP:
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dev_dbg(dpu->dev, "FetchDecode%d with arbitrary warping and "
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"fractional plane(8 layers)\n", fu->id);
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break;
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case FETCHTYPE__ECO:
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dev_dbg(dpu->dev, "FetchDecode%d with minimum feature set for "
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"alpha, chroma and coordinate planes\n",
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fu->id);
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break;
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case FETCHTYPE__PERSP:
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dev_dbg(dpu->dev, "FetchDecode%d with affine, perspective and "
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"arbitrary warping\n", fu->id);
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break;
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case FETCHTYPE__ROT:
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dev_dbg(dpu->dev, "FetchDecode%d with affine and arbitrary "
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"warping\n", fu->id);
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break;
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case FETCHTYPE__DECODEL:
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dev_dbg(dpu->dev, "FetchDecode%d with RL and RLAD decoder, "
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"reduced feature set\n", fu->id);
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break;
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case FETCHTYPE__LAYERL:
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dev_dbg(dpu->dev, "FetchDecode%d with fractional "
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"plane(8 layers), reduced feature set\n",
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fu->id);
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break;
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case FETCHTYPE__ROTL:
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dev_dbg(dpu->dev, "FetchDecode%d with affine and arbitrary "
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"warping, reduced feature set\n", fu->id);
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break;
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default:
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dev_warn(dpu->dev, "Invalid fetch type %u for FetchDecode%d\n",
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val, fu->id);
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return -EINVAL;
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}
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|
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*type = val;
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return 0;
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}
|
|
EXPORT_SYMBOL_GPL(fetchdecode_fetchtype);
|
|
|
|
shadow_load_req_t fetchdecode_to_shdldreq_t(struct dpu_fetchunit *fu)
|
|
{
|
|
shadow_load_req_t t = 0;
|
|
|
|
switch (fu->id) {
|
|
case 0:
|
|
t = SHLDREQID_FETCHDECODE0;
|
|
break;
|
|
case 1:
|
|
t = SHLDREQID_FETCHDECODE1;
|
|
break;
|
|
case 2:
|
|
t = SHLDREQID_FETCHDECODE2;
|
|
break;
|
|
case 3:
|
|
t = SHLDREQID_FETCHDECODE3;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return t;
|
|
}
|
|
EXPORT_SYMBOL_GPL(fetchdecode_to_shdldreq_t);
|
|
|
|
u32 fetchdecode_get_vproc_mask(struct dpu_fetchunit *fu)
|
|
{
|
|
struct dpu_soc *dpu = fu->dpu;
|
|
const struct dpu_devtype *devtype = dpu->devtype;
|
|
|
|
return devtype->version == DPU_V1 ?
|
|
fd_vproc_cap_v1[fu->id] : fd_vproc_cap_v2[fu->id];
|
|
}
|
|
EXPORT_SYMBOL_GPL(fetchdecode_get_vproc_mask);
|
|
|
|
struct dpu_fetchunit *fetchdecode_get_fetcheco(struct dpu_fetchunit *fu)
|
|
{
|
|
struct dpu_soc *dpu = fu->dpu;
|
|
|
|
switch (fu->id) {
|
|
case 0:
|
|
case 1:
|
|
return dpu->fe_priv[fu->id];
|
|
case 2:
|
|
case 3:
|
|
/* TODO: for DPU v1, add FetchEco2 support */
|
|
return dpu->fe_priv[fu->id - 2];
|
|
default:
|
|
WARN_ON(1);
|
|
}
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
EXPORT_SYMBOL_GPL(fetchdecode_get_fetcheco);
|
|
|
|
bool fetchdecode_need_fetcheco(struct dpu_fetchunit *fu, u32 fmt)
|
|
{
|
|
struct dpu_fetchunit *fe = fetchdecode_get_fetcheco(fu);
|
|
|
|
if (IS_ERR_OR_NULL(fe))
|
|
return false;
|
|
|
|
switch (fmt) {
|
|
case DRM_FORMAT_NV12:
|
|
case DRM_FORMAT_NV21:
|
|
case DRM_FORMAT_NV16:
|
|
case DRM_FORMAT_NV61:
|
|
case DRM_FORMAT_NV24:
|
|
case DRM_FORMAT_NV42:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL_GPL(fetchdecode_need_fetcheco);
|
|
|
|
struct dpu_hscaler *fetchdecode_get_hscaler(struct dpu_fetchunit *fu)
|
|
{
|
|
struct dpu_soc *dpu = fu->dpu;
|
|
|
|
switch (fu->id) {
|
|
case 0:
|
|
case 2:
|
|
return dpu->hs_priv[0];
|
|
case 1:
|
|
case 3:
|
|
return dpu->hs_priv[1];
|
|
default:
|
|
WARN_ON(1);
|
|
}
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
EXPORT_SYMBOL_GPL(fetchdecode_get_hscaler);
|
|
|
|
struct dpu_vscaler *fetchdecode_get_vscaler(struct dpu_fetchunit *fu)
|
|
{
|
|
struct dpu_soc *dpu = fu->dpu;
|
|
|
|
switch (fu->id) {
|
|
case 0:
|
|
case 2:
|
|
return dpu->vs_priv[0];
|
|
case 1:
|
|
case 3:
|
|
return dpu->vs_priv[1];
|
|
default:
|
|
WARN_ON(1);
|
|
}
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
EXPORT_SYMBOL_GPL(fetchdecode_get_vscaler);
|
|
|
|
struct dpu_fetchunit *dpu_fd_get(struct dpu_soc *dpu, int id)
|
|
{
|
|
struct dpu_fetchunit *fu;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(fd_ids); i++)
|
|
if (fd_ids[i] == id)
|
|
break;
|
|
|
|
if (i == ARRAY_SIZE(fd_ids))
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
fu = dpu->fd_priv[i];
|
|
|
|
mutex_lock(&fu->mutex);
|
|
|
|
if (fu->inuse) {
|
|
fu = ERR_PTR(-EBUSY);
|
|
goto out;
|
|
}
|
|
|
|
fu->inuse = true;
|
|
out:
|
|
mutex_unlock(&fu->mutex);
|
|
|
|
return fu;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dpu_fd_get);
|
|
|
|
void dpu_fd_put(struct dpu_fetchunit *fu)
|
|
{
|
|
mutex_lock(&fu->mutex);
|
|
|
|
fu->inuse = false;
|
|
|
|
mutex_unlock(&fu->mutex);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dpu_fd_put);
|
|
|
|
static const struct dpu_fetchunit_ops fd_ops = {
|
|
.set_burstlength = fetchunit_set_burstlength,
|
|
.set_baseaddress = fetchdecode_set_baseaddress,
|
|
.set_src_bpp = fetchdecode_set_src_bpp,
|
|
.set_src_stride = fetchdecode_set_src_stride,
|
|
.set_src_buf_dimensions = fetchdecode_set_src_buf_dimensions,
|
|
.set_fmt = fetchdecode_set_fmt,
|
|
.enable_src_buf = fetchdecode_enable_src_buf,
|
|
.disable_src_buf = fetchdecode_disable_src_buf,
|
|
.is_enabled = fetchdecode_is_enabled,
|
|
.set_framedimensions = fetchdecode_set_framedimensions,
|
|
.set_controltrigger = fetchdecode_set_controltrigger,
|
|
.get_stream_id = fetchunit_get_stream_id,
|
|
.set_stream_id = fetchunit_set_stream_id,
|
|
.pin_off = fetchunit_pin_off,
|
|
.unpin_off = fetchunit_unpin_off,
|
|
.is_pinned_off = fetchunit_is_pinned_off,
|
|
};
|
|
|
|
void _dpu_fd_init(struct dpu_soc *dpu, unsigned int id)
|
|
{
|
|
struct dpu_fetchunit *fu;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(fd_ids); i++)
|
|
if (fd_ids[i] == id)
|
|
break;
|
|
|
|
if (WARN_ON(i == ARRAY_SIZE(fd_ids)))
|
|
return;
|
|
|
|
fu = dpu->fd_priv[i];
|
|
|
|
fetchdecode_pixengcfg_dynamic_src_sel(fu, FD_SRC_DISABLE);
|
|
fetchunit_baddr_autoupdate(fu, 0x0);
|
|
fetchunit_shden(fu, true);
|
|
|
|
mutex_lock(&fu->mutex);
|
|
dpu_fu_write(fu, SETNUMBUFFERS(16) | SETBURSTLENGTH(16),
|
|
BURSTBUFFERMANAGEMENT);
|
|
mutex_unlock(&fu->mutex);
|
|
}
|
|
|
|
int dpu_fd_init(struct dpu_soc *dpu, unsigned int id,
|
|
unsigned long pec_base, unsigned long base)
|
|
{
|
|
struct dpu_fetchdecode *fd;
|
|
struct dpu_fetchunit *fu;
|
|
int ret, i;
|
|
|
|
fd = devm_kzalloc(dpu->dev, sizeof(*fd), GFP_KERNEL);
|
|
if (!fd)
|
|
return -ENOMEM;
|
|
|
|
fu = &fd->fu;
|
|
dpu->fd_priv[id] = fu;
|
|
|
|
fu->pec_base = devm_ioremap(dpu->dev, pec_base, SZ_16);
|
|
if (!fu->pec_base)
|
|
return -ENOMEM;
|
|
|
|
fu->base = devm_ioremap(dpu->dev, base, SZ_1K);
|
|
if (!fu->base)
|
|
return -ENOMEM;
|
|
|
|
fu->dpu = dpu;
|
|
fu->id = id;
|
|
fu->type = FU_T_FD;
|
|
fu->ops = &fd_ops;
|
|
fu->name = "fetchdecode";
|
|
for (i = 0; i < ARRAY_SIZE(fd_ids); i++) {
|
|
if (fd_ids[i] == id) {
|
|
fd->shdlreq = fd_shdlreqs[i];
|
|
break;
|
|
}
|
|
}
|
|
mutex_init(&fu->mutex);
|
|
|
|
ret = fetchdecode_pixengcfg_dynamic_src_sel(fu, FD_SRC_DISABLE);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = fetchdecode_fetchtype(fu, &fd->fetchtype);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
_dpu_fd_init(dpu, id);
|
|
|
|
return 0;
|
|
}
|