![Linus Torvalds](/assets/img/avatar_default.png)
* 'gpio/next' of git://git.secretlab.ca/git/linux-2.6: (61 commits) gpio/mxc/mxs: fix build error introduced by the irq_gc_ack() renaming mcp23s08: add i2c support mcp23s08: isolate spi specific parts mcp23s08: get rid of setup/teardown callbacks gpio/tegra: dt: add binding for gpio polarity mcp23s08: remove unused work queue gpio/da9052: remove a redundant assignment for gpio->da9052 gpio/mxc: add device tree probe support ARM: mxc: use ARCH_NR_GPIOS to define gpio number gpio/mxc: get rid of the uses of cpu_is_mx() gpio/mxc: add missing initialization of basic_mmio_gpio shadow variables gpio: Move mpc5200 gpio driver to drivers/gpio GPIO: DA9052 GPIO module v3 gpio/tegra: Use engineering names in DT compatible property of/gpio: Add new method for getting gpios under different property names gpio/dt: Refine GPIO device tree binding gpio/ml-ioh: fix off-by-one for displaying variable i in dev_err gpio/pca953x: Deprecate meaningless device-tree bindings gpio/pca953x: Remove dynamic platform data pointer gpio/pca953x: Fix IRQ support. ...
459 lines
11 KiB
C
459 lines
11 KiB
C
/*
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* Moorestown platform Langwell chip GPIO driver
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*
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* Copyright (c) 2008 - 2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Supports:
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* Moorestown platform Langwell chip.
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* Medfield platform Penwell chip.
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* Whitney point.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/stddef.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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/*
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* Langwell chip has 64 pins and thus there are 2 32bit registers to control
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* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
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* registers to control them, so we only define the order here instead of a
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* structure, to get a bit offset for a pin (use GPDR as an example):
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*
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* nreg = ngpio / 32;
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* reg = offset / 32;
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* bit = offset % 32;
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* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
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*
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* so the bit of reg_addr is to control pin offset's GPDR feature
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*/
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enum GPIO_REG {
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GPLR = 0, /* pin level read-only */
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GPDR, /* pin direction */
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GPSR, /* pin set */
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GPCR, /* pin clear */
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GRER, /* rising edge detect */
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GFER, /* falling edge detect */
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GEDR, /* edge detect result */
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};
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struct lnw_gpio {
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struct gpio_chip chip;
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void *reg_base;
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spinlock_t lock;
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unsigned irq_base;
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struct pci_dev *pdev;
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};
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static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
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enum GPIO_REG reg_type)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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unsigned nreg = chip->ngpio / 32;
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u8 reg = offset / 32;
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void __iomem *ptr;
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ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
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return ptr;
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}
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static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *gplr = gpio_reg(chip, offset, GPLR);
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return readl(gplr) & BIT(offset % 32);
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}
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static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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void __iomem *gpsr, *gpcr;
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if (value) {
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gpsr = gpio_reg(chip, offset, GPSR);
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writel(BIT(offset % 32), gpsr);
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} else {
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gpcr = gpio_reg(chip, offset, GPCR);
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writel(BIT(offset % 32), gpcr);
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}
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}
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static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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u32 value;
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unsigned long flags;
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if (lnw->pdev)
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pm_runtime_get(&lnw->pdev->dev);
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spin_lock_irqsave(&lnw->lock, flags);
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value = readl(gpdr);
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value &= ~BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&lnw->lock, flags);
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if (lnw->pdev)
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pm_runtime_put(&lnw->pdev->dev);
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return 0;
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}
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static int lnw_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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unsigned long flags;
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lnw_gpio_set(chip, offset, value);
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if (lnw->pdev)
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pm_runtime_get(&lnw->pdev->dev);
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spin_lock_irqsave(&lnw->lock, flags);
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value = readl(gpdr);
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value |= BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&lnw->lock, flags);
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if (lnw->pdev)
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pm_runtime_put(&lnw->pdev->dev);
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return 0;
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}
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static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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return lnw->irq_base + offset;
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}
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static int lnw_irq_type(struct irq_data *d, unsigned type)
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{
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struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
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u32 gpio = d->irq - lnw->irq_base;
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unsigned long flags;
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u32 value;
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void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
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void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
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if (gpio >= lnw->chip.ngpio)
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return -EINVAL;
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if (lnw->pdev)
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pm_runtime_get(&lnw->pdev->dev);
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spin_lock_irqsave(&lnw->lock, flags);
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if (type & IRQ_TYPE_EDGE_RISING)
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value = readl(grer) | BIT(gpio % 32);
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else
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value = readl(grer) & (~BIT(gpio % 32));
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writel(value, grer);
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if (type & IRQ_TYPE_EDGE_FALLING)
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value = readl(gfer) | BIT(gpio % 32);
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else
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value = readl(gfer) & (~BIT(gpio % 32));
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writel(value, gfer);
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spin_unlock_irqrestore(&lnw->lock, flags);
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if (lnw->pdev)
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pm_runtime_put(&lnw->pdev->dev);
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return 0;
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}
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static void lnw_irq_unmask(struct irq_data *d)
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{
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}
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static void lnw_irq_mask(struct irq_data *d)
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{
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}
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static struct irq_chip lnw_irqchip = {
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.name = "LNW-GPIO",
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.irq_mask = lnw_irq_mask,
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.irq_unmask = lnw_irq_unmask,
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.irq_set_type = lnw_irq_type,
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};
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static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
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static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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u32 base, gpio, mask;
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unsigned long pending;
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void __iomem *gedr;
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/* check GPIO controller to check which pin triggered the interrupt */
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for (base = 0; base < lnw->chip.ngpio; base += 32) {
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gedr = gpio_reg(&lnw->chip, base, GEDR);
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pending = readl(gedr);
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while (pending) {
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gpio = __ffs(pending);
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mask = BIT(gpio);
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pending &= ~mask;
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/* Clear before handling so we can't lose an edge */
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writel(mask, gedr);
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generic_handle_irq(lnw->irq_base + base + gpio);
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}
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}
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chip->irq_eoi(data);
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}
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#ifdef CONFIG_PM
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static int lnw_gpio_runtime_resume(struct device *dev)
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{
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return 0;
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}
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static int lnw_gpio_runtime_suspend(struct device *dev)
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{
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return 0;
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}
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static int lnw_gpio_runtime_idle(struct device *dev)
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{
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int err = pm_schedule_suspend(dev, 500);
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if (!err)
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return 0;
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return -EBUSY;
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}
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#else
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#define lnw_gpio_runtime_suspend NULL
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#define lnw_gpio_runtime_resume NULL
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#define lnw_gpio_runtime_idle NULL
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#endif
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static const struct dev_pm_ops lnw_gpio_pm_ops = {
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.runtime_suspend = lnw_gpio_runtime_suspend,
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.runtime_resume = lnw_gpio_runtime_resume,
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.runtime_idle = lnw_gpio_runtime_idle,
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};
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static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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void *base;
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int i;
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resource_size_t start, len;
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struct lnw_gpio *lnw;
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u32 irq_base;
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u32 gpio_base;
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int retval = 0;
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retval = pci_enable_device(pdev);
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if (retval)
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goto done;
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retval = pci_request_regions(pdev, "langwell_gpio");
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if (retval) {
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dev_err(&pdev->dev, "error requesting resources\n");
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goto err2;
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}
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/* get the irq_base from bar1 */
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start = pci_resource_start(pdev, 1);
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len = pci_resource_len(pdev, 1);
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base = ioremap_nocache(start, len);
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if (!base) {
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dev_err(&pdev->dev, "error mapping bar1\n");
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goto err3;
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}
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irq_base = *(u32 *)base;
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gpio_base = *((u32 *)base + 1);
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/* release the IO mapping, since we already get the info from bar1 */
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iounmap(base);
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/* get the register base from bar0 */
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start = pci_resource_start(pdev, 0);
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len = pci_resource_len(pdev, 0);
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base = ioremap_nocache(start, len);
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if (!base) {
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dev_err(&pdev->dev, "error mapping bar0\n");
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retval = -EFAULT;
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goto err3;
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}
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lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
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if (!lnw) {
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dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
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retval = -ENOMEM;
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goto err4;
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}
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lnw->reg_base = base;
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lnw->irq_base = irq_base;
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lnw->chip.label = dev_name(&pdev->dev);
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lnw->chip.direction_input = lnw_gpio_direction_input;
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lnw->chip.direction_output = lnw_gpio_direction_output;
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lnw->chip.get = lnw_gpio_get;
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lnw->chip.set = lnw_gpio_set;
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lnw->chip.to_irq = lnw_gpio_to_irq;
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lnw->chip.base = gpio_base;
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lnw->chip.ngpio = id->driver_data;
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lnw->chip.can_sleep = 0;
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lnw->pdev = pdev;
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pci_set_drvdata(pdev, lnw);
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retval = gpiochip_add(&lnw->chip);
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if (retval) {
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dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
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goto err5;
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}
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irq_set_handler_data(pdev->irq, lnw);
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irq_set_chained_handler(pdev->irq, lnw_irq_handler);
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for (i = 0; i < lnw->chip.ngpio; i++) {
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irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
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handle_simple_irq, "demux");
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irq_set_chip_data(i + lnw->irq_base, lnw);
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}
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spin_lock_init(&lnw->lock);
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_allow(&pdev->dev);
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goto done;
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err5:
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kfree(lnw);
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err4:
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iounmap(base);
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err3:
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pci_release_regions(pdev);
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err2:
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pci_disable_device(pdev);
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done:
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return retval;
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}
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static struct pci_driver lnw_gpio_driver = {
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.name = "langwell_gpio",
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.id_table = lnw_gpio_ids,
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.probe = lnw_gpio_probe,
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.driver = {
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.pm = &lnw_gpio_pm_ops,
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},
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};
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static int __devinit wp_gpio_probe(struct platform_device *pdev)
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{
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struct lnw_gpio *lnw;
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struct gpio_chip *gc;
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struct resource *rc;
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int retval = 0;
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rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!rc)
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return -EINVAL;
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lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
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if (!lnw) {
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dev_err(&pdev->dev,
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"can't allocate whitneypoint_gpio chip data\n");
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return -ENOMEM;
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}
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lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
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if (lnw->reg_base == NULL) {
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retval = -EINVAL;
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goto err_kmalloc;
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}
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spin_lock_init(&lnw->lock);
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gc = &lnw->chip;
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gc->label = dev_name(&pdev->dev);
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gc->owner = THIS_MODULE;
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gc->direction_input = lnw_gpio_direction_input;
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gc->direction_output = lnw_gpio_direction_output;
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gc->get = lnw_gpio_get;
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gc->set = lnw_gpio_set;
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gc->to_irq = NULL;
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gc->base = 0;
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gc->ngpio = 64;
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gc->can_sleep = 0;
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retval = gpiochip_add(gc);
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if (retval) {
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dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
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retval);
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goto err_ioremap;
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}
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platform_set_drvdata(pdev, lnw);
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return 0;
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err_ioremap:
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iounmap(lnw->reg_base);
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err_kmalloc:
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kfree(lnw);
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return retval;
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}
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static int __devexit wp_gpio_remove(struct platform_device *pdev)
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{
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struct lnw_gpio *lnw = platform_get_drvdata(pdev);
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int err;
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err = gpiochip_remove(&lnw->chip);
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if (err)
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dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
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iounmap(lnw->reg_base);
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kfree(lnw);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver wp_gpio_driver = {
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.probe = wp_gpio_probe,
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.remove = __devexit_p(wp_gpio_remove),
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.driver = {
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.name = "wp_gpio",
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.owner = THIS_MODULE,
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},
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};
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static int __init lnw_gpio_init(void)
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{
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int ret;
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ret = pci_register_driver(&lnw_gpio_driver);
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if (ret < 0)
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return ret;
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ret = platform_driver_register(&wp_gpio_driver);
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if (ret < 0)
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pci_unregister_driver(&lnw_gpio_driver);
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return ret;
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}
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device_initcall(lnw_gpio_init);
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