206af3d97f
commit 0b0408745e upstream.
LPDDR memories can only handle up to 400 uncontrolled power off. Ensure the
proper power off sequence is used before shutting down the platform.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
237 lines
6.1 KiB
C
237 lines
6.1 KiB
C
/*
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* Atmel AT91 SAM9 SoCs reset code
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*
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* Copyright (C) 2007 Atmel Corporation.
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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* Copyright (C) 2014 Free Electrons
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/printk.h>
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#include <soc/at91/at91sam9_ddrsdr.h>
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#define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
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#define AT91_SHDW_SHDW BIT(0) /* Shut Down command */
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#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
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#define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
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#define AT91_SHDW_WKMODE0 GENMASK(2, 0) /* Wake-up 0 Mode Selection */
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#define AT91_SHDW_CPTWK0_MAX 0xf /* Maximum Counter On Wake Up 0 */
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#define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
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#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
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#define AT91_SHDW_RTTWKEN BIT(16) /* Real Time Timer Wake-up Enable */
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#define AT91_SHDW_RTCWKEN BIT(17) /* Real Time Clock Wake-up Enable */
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#define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
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#define AT91_SHDW_WAKEUP0 BIT(0) /* Wake-up 0 Status */
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#define AT91_SHDW_RTTWK BIT(16) /* Real-time Timer Wake-up */
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#define AT91_SHDW_RTCWK BIT(17) /* Real-time Clock Wake-up [SAM9RL] */
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enum wakeup_type {
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AT91_SHDW_WKMODE0_NONE = 0,
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AT91_SHDW_WKMODE0_HIGH = 1,
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AT91_SHDW_WKMODE0_LOW = 2,
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AT91_SHDW_WKMODE0_ANYLEVEL = 3,
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};
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static const char *shdwc_wakeup_modes[] = {
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[AT91_SHDW_WKMODE0_NONE] = "none",
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[AT91_SHDW_WKMODE0_HIGH] = "high",
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[AT91_SHDW_WKMODE0_LOW] = "low",
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[AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
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};
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static void __iomem *at91_shdwc_base;
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static struct clk *sclk;
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static void __iomem *mpddrc_base;
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static void __init at91_wakeup_status(void)
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{
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u32 reg = readl(at91_shdwc_base + AT91_SHDW_SR);
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char *reason = "unknown";
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/* Simple power-on, just bail out */
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if (!reg)
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return;
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if (reg & AT91_SHDW_RTTWK)
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reason = "RTT";
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else if (reg & AT91_SHDW_RTCWK)
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reason = "RTC";
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pr_info("AT91: Wake-Up source: %s\n", reason);
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}
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static void at91_poweroff(void)
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{
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writel(AT91_SHDW_KEY | AT91_SHDW_SHDW, at91_shdwc_base + AT91_SHDW_CR);
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}
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static void at91_lpddr_poweroff(void)
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{
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asm volatile(
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/* Align to cache lines */
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".balign 32\n\t"
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/* Ensure AT91_SHDW_CR is in the TLB by reading it */
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" ldr r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
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/* Power down SDRAM0 */
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" str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
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/* Shutdown CPU */
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" str %3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
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" b .\n\t"
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:
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: "r" (mpddrc_base),
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"r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
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"r" (at91_shdwc_base),
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"r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
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: "r0");
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}
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static int at91_poweroff_get_wakeup_mode(struct device_node *np)
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{
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const char *pm;
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unsigned int i;
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int err;
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err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
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if (err < 0)
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return AT91_SHDW_WKMODE0_ANYLEVEL;
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for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
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if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
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return i;
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return -ENODEV;
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}
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static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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int wakeup_mode;
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u32 mode = 0, tmp;
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wakeup_mode = at91_poweroff_get_wakeup_mode(np);
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if (wakeup_mode < 0) {
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dev_warn(&pdev->dev, "shdwc unknown wakeup mode\n");
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return;
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}
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if (!of_property_read_u32(np, "atmel,wakeup-counter", &tmp)) {
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if (tmp > AT91_SHDW_CPTWK0_MAX) {
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dev_warn(&pdev->dev,
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"shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
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tmp, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
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tmp = AT91_SHDW_CPTWK0_MAX;
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}
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mode |= AT91_SHDW_CPTWK0_(tmp);
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}
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if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
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mode |= AT91_SHDW_RTCWKEN;
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if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
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mode |= AT91_SHDW_RTTWKEN;
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writel(wakeup_mode | mode, at91_shdwc_base + AT91_SHDW_MR);
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}
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static int __init at91_poweroff_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct device_node *np;
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u32 ddr_type;
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int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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at91_shdwc_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(at91_shdwc_base)) {
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dev_err(&pdev->dev, "Could not map reset controller address\n");
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return PTR_ERR(at91_shdwc_base);
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}
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sclk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(sclk))
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return PTR_ERR(sclk);
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ret = clk_prepare_enable(sclk);
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if (ret) {
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dev_err(&pdev->dev, "Could not enable slow clock\n");
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return ret;
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}
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at91_wakeup_status();
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if (pdev->dev.of_node)
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at91_poweroff_dt_set_wakeup_mode(pdev);
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pm_power_off = at91_poweroff;
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np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
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if (!np)
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return 0;
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mpddrc_base = of_iomap(np, 0);
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of_node_put(np);
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if (!mpddrc_base)
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return 0;
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ddr_type = readl(mpddrc_base + AT91_DDRSDRC_MDR) & AT91_DDRSDRC_MD;
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if ((ddr_type == AT91_DDRSDRC_MD_LPDDR2) ||
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(ddr_type == AT91_DDRSDRC_MD_LPDDR3))
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pm_power_off = at91_lpddr_poweroff;
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else
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iounmap(mpddrc_base);
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return 0;
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}
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static int __exit at91_poweroff_remove(struct platform_device *pdev)
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{
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if (pm_power_off == at91_poweroff ||
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pm_power_off == at91_lpddr_poweroff)
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pm_power_off = NULL;
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clk_disable_unprepare(sclk);
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return 0;
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}
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static const struct of_device_id at91_ramc_of_match[] = {
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{ .compatible = "atmel,sama5d3-ddramc", },
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{ /* sentinel */ }
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};
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static const struct of_device_id at91_poweroff_of_match[] = {
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{ .compatible = "atmel,at91sam9260-shdwc", },
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{ .compatible = "atmel,at91sam9rl-shdwc", },
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{ .compatible = "atmel,at91sam9x5-shdwc", },
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{ /*sentinel*/ }
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};
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static struct platform_driver at91_poweroff_driver = {
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.remove = __exit_p(at91_poweroff_remove),
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.driver = {
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.name = "at91-poweroff",
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.of_match_table = at91_poweroff_of_match,
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},
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};
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module_platform_driver_probe(at91_poweroff_driver, at91_poweroff_probe);
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MODULE_AUTHOR("Atmel Corporation");
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MODULE_DESCRIPTION("Shutdown driver for Atmel SoCs");
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MODULE_LICENSE("GPL v2");
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