414 lines
10 KiB
C
414 lines
10 KiB
C
/**
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* @file bd71837.h ROHM BD71837MWV header file
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*
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* Copyright 2017
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* @author cpham2403@gmail.com
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*/
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#ifndef __LINUX_MFD_BD71837_H
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#define __LINUX_MFD_BD71837_H
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#include <linux/regmap.h>
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enum {
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BD71837_BUCK1 = 0,
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BD71837_BUCK2,
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BD71837_BUCK3,
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BD71837_BUCK4,
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BD71837_BUCK5,
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BD71837_BUCK6,
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BD71837_BUCK7,
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BD71837_BUCK8,
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// General Purpose
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BD71837_LDO1,
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BD71837_LDO2,
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BD71837_LDO3,
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BD71837_LDO4,
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BD71837_LDO5,
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BD71837_LDO6,
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BD71837_LDO7,
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BD71837_REGULATOR_CNT,
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};
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#define BD71837_SUPPLY_STATE_ENABLED 0x1
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#define BD71837_BUCK1_VOLTAGE_NUM 0x40
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#define BD71837_BUCK2_VOLTAGE_NUM 0x40
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#define BD71837_BUCK3_VOLTAGE_NUM 0x40
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#define BD71837_BUCK4_VOLTAGE_NUM 0x40
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#define BD71837_BUCK5_VOLTAGE_NUM 0x08
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#define BD71837_BUCK6_VOLTAGE_NUM 0x04
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#define BD71837_BUCK7_VOLTAGE_NUM 0x08
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#define BD71837_BUCK8_VOLTAGE_NUM 0x40
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#define BD71837_LDO1_VOLTAGE_NUM 0x04
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#define BD71837_LDO2_VOLTAGE_NUM 0x02
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#define BD71837_LDO3_VOLTAGE_NUM 0x10
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#define BD71837_LDO4_VOLTAGE_NUM 0x10
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#define BD71837_LDO5_VOLTAGE_NUM 0x10
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#define BD71837_LDO6_VOLTAGE_NUM 0x10
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#define BD71837_LDO7_VOLTAGE_NUM 0x10
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enum {
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BD71837_REG_REV = 0x00,
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BD71837_REG_SWRESET = 0x01,
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BD71837_REG_I2C_DEV = 0x02,
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BD71837_REG_PWRCTRL0 = 0x03,
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BD71837_REG_PWRCTRL1 = 0x04,
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BD71837_REG_BUCK1_CTRL = 0x05,
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BD71837_REG_BUCK2_CTRL = 0x06,
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BD71837_REG_BUCK3_CTRL = 0x07,
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BD71837_REG_BUCK4_CTRL = 0x08,
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BD71837_REG_BUCK5_CTRL = 0x09,
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BD71837_REG_BUCK6_CTRL = 0x0A,
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BD71837_REG_BUCK7_CTRL = 0x0B,
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BD71837_REG_BUCK8_CTRL = 0x0C,
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BD71837_REG_BUCK1_VOLT_RUN = 0x0D,
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BD71837_REG_BUCK1_VOLT_IDLE = 0x0E,
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BD71837_REG_BUCK1_VOLT_SUSP = 0x0F,
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BD71837_REG_BUCK2_VOLT_RUN = 0x10,
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BD71837_REG_BUCK2_VOLT_IDLE = 0x11,
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BD71837_REG_BUCK3_VOLT_RUN = 0x12,
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BD71837_REG_BUCK4_VOLT_RUN = 0x13,
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BD71837_REG_BUCK5_VOLT = 0x14,
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BD71837_REG_BUCK6_VOLT = 0x15,
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BD71837_REG_BUCK7_VOLT = 0x16,
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BD71837_REG_BUCK8_VOLT = 0x17,
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BD71837_REG_LDO1_VOLT = 0x18,
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BD71837_REG_LDO2_VOLT = 0x19,
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BD71837_REG_LDO3_VOLT = 0x1A,
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BD71837_REG_LDO4_VOLT = 0x1B,
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BD71837_REG_LDO5_VOLT = 0x1C,
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BD71837_REG_LDO6_VOLT = 0x1D,
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BD71837_REG_LDO7_VOLT = 0x1E,
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BD71837_REG_TRANS_COND0 = 0x1F,
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BD71837_REG_TRANS_COND1 = 0x20,
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BD71837_REG_VRFAULTEN = 0x21,
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BD71837_REG_MVRFLTMASK0 = 0x22,
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BD71837_REG_MVRFLTMASK1 = 0x23,
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BD71837_REG_MVRFLTMASK2 = 0x24,
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BD71837_REG_RCVCFG = 0x25,
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BD71837_REG_RCVNUM = 0x26,
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BD71837_REG_PWRONCONFIG0 = 0x27,
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BD71837_REG_PWRONCONFIG1 = 0x28,
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BD71837_REG_RESETSRC = 0x29,
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BD71837_REG_MIRQ = 0x2A,
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BD71837_REG_IRQ = 0x2B,
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BD71837_REG_IN_MON = 0x2C,
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BD71837_REG_POW_STATE = 0x2D,
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BD71837_REG_OUT32K = 0x2E,
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BD71837_REG_REGLOCK = 0x2F,
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BD71837_REG_OTPVER = 0xFF,
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BD71837_MAX_REGISTER = 0x100,
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};
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/* BD71837_REG_BUCK1_CTRL bits */
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#define BUCK1_RAMPRATE_MASK 0xC0
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#define BUCK1_RAMPRATE_10P00MV 0x0
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#define BUCK1_RAMPRATE_5P00MV 0x1
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#define BUCK1_RAMPRATE_2P50MV 0x2
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#define BUCK1_RAMPRATE_1P25MV 0x3
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#define BUCK1_SEL 0x02
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#define BUCK1_EN 0x01
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/* BD71837_REG_BUCK2_CTRL bits */
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#define BUCK2_RAMPRATE_MASK 0xC0
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#define BUCK2_RAMPRATE_10P00MV 0x0
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#define BUCK2_RAMPRATE_5P00MV 0x1
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#define BUCK2_RAMPRATE_2P50MV 0x2
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#define BUCK2_RAMPRATE_1P25MV 0x3
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#define BUCK2_SEL 0x02
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#define BUCK2_EN 0x01
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/* BD71837_REG_BUCK3_CTRL bits */
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#define BUCK3_RAMPRATE_MASK 0xC0
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#define BUCK3_RAMPRATE_10P00MV 0x0
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#define BUCK3_RAMPRATE_5P00MV 0x1
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#define BUCK3_RAMPRATE_2P50MV 0x2
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#define BUCK3_RAMPRATE_1P25MV 0x3
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#define BUCK3_SEL 0x02
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#define BUCK3_EN 0x01
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/* BD71837_REG_BUCK4_CTRL bits */
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#define BUCK4_RAMPRATE_MASK 0xC0
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#define BUCK4_RAMPRATE_10P00MV 0x0
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#define BUCK4_RAMPRATE_5P00MV 0x1
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#define BUCK4_RAMPRATE_2P50MV 0x2
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#define BUCK4_RAMPRATE_1P25MV 0x3
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#define BUCK4_SEL 0x02
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#define BUCK4_EN 0x01
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/* BD71837_REG_BUCK5_CTRL bits */
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#define BUCK5_SEL 0x02
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#define BUCK5_EN 0x01
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/* BD71837_REG_BUCK6_CTRL bits */
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#define BUCK6_SEL 0x02
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#define BUCK6_EN 0x01
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/* BD71837_REG_BUCK7_CTRL bits */
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#define BUCK7_SEL 0x02
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#define BUCK7_EN 0x01
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/* BD71837_REG_BUCK8_CTRL bits */
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#define BUCK8_SEL 0x02
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#define BUCK8_EN 0x01
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/* BD71837_REG_BUCK1_VOLT_RUN bits */
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#define BUCK1_RUN_MASK 0x3F
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#define BUCK1_RUN_DEFAULT 0x14
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/* BD71837_REG_BUCK1_VOLT_SUSP bits */
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#define BUCK1_SUSP_MASK 0x3F
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#define BUCK1_SUSP_DEFAULT 0x14
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/* BD71837_REG_BUCK1_VOLT_IDLE bits */
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#define BUCK1_IDLE_MASK 0x3F
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#define BUCK1_IDLE_DEFAULT 0x14
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/* BD71837_REG_BUCK2_VOLT_RUN bits */
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#define BUCK2_RUN_MASK 0x3F
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#define BUCK2_RUN_DEFAULT 0x1E
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/* BD71837_REG_BUCK2_VOLT_IDLE bits */
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#define BUCK2_IDLE_MASK 0x3F
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#define BUCK2_IDLE_DEFAULT 0x14
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/* BD71837_REG_BUCK3_VOLT_RUN bits */
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#define BUCK3_RUN_MASK 0x3F
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#define BUCK3_RUN_DEFAULT 0x1E
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/* BD71837_REG_BUCK4_VOLT_RUN bits */
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#define BUCK4_RUN_MASK 0x3F
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#define BUCK4_RUN_DEFAULT 0x1E
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/* BD71837_REG_BUCK5_VOLT bits */
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#define BUCK5_MASK 0x07
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#define BUCK5_DEFAULT 0x02
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/* BD71837_REG_BUCK6_VOLT bits */
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#define BUCK6_MASK 0x03
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#define BUCK6_DEFAULT 0x03
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/* BD71837_REG_BUCK7_VOLT bits */
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#define BUCK7_MASK 0x07
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#define BUCK7_DEFAULT 0x03
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/* BD71837_REG_BUCK8_VOLT bits */
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#define BUCK8_MASK 0x3F
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#define BUCK8_DEFAULT 0x1E
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/* BD71837_REG_IRQ bits */
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#define IRQ_SWRST 0x40
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#define IRQ_PWRON_S 0x20
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#define IRQ_PWRON_L 0x10
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#define IRQ_PWRON 0x08
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#define IRQ_WDOG 0x04
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#define IRQ_ON_REQ 0x02
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#define IRQ_STBY_REQ 0x01
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/* BD71837_REG_OUT32K bits */
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#define OUT32K_EN 0x01
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/* BD71837 interrupt masks */
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enum {
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BD71837_INT_MASK = 0x7F,
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};
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/* BD71837 interrupt irqs */
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enum {
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BD71837_IRQ = 0x0,
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};
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/* BD71837_REG_LDO1_VOLT bits */
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#define LDO1_SEL 0x80
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#define LDO1_EN 0x40
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#define LDO1_MASK 0x03
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/* BD71837_REG_LDO2_VOLT bits */
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#define LDO2_SEL 0x80
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#define LDO2_EN 0x40
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/* BD71837_REG_LDO3_VOLT bits */
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#define LDO3_SEL 0x80
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#define LDO3_EN 0x40
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#define LDO3_MASK 0x0F
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/* BD71837_REG_LDO4_VOLT bits */
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#define LDO4_SEL 0x80
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#define LDO4_EN 0x40
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#define LDO4_MASK 0x0F
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/* BD71837_REG_LDO5_VOLT bits */
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#define LDO5_EN 0x40
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#define LDO5_MASK 0x0F
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/* BD71837_REG_LDO6_VOLT bits */
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#define LDO6_EN 0x40
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#define LDO6_MASK 0x0F
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/* BD71837_REG_LDO7_VOLT bits */
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#define LDO7_EN 0x40
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#define LDO7_MASK 0x0F
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/** @brief charge state enumuration */
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enum CHG_STATE {
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CHG_STATE_SUSPEND = 0x0, /**< suspend state */
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CHG_STATE_TRICKLE_CHARGE, /**< trickle charge state */
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CHG_STATE_PRE_CHARGE, /**< precharge state */
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CHG_STATE_FAST_CHARGE, /**< fast charge state */
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CHG_STATE_TOP_OFF, /**< top off state */
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CHG_STATE_DONE, /**< charge complete */
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};
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struct bd71837;
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/**
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* @brief Board platform data may be used to initialize regulators.
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*/
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struct bd71837_board {
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struct regulator_init_data *init_data[BD71837_REGULATOR_CNT];
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/**< regulator initialize data */
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int gpio_intr; /**< gpio connected to bd71837 INTB */
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int irq_base; /**< bd71837 sub irqs base # */
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};
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/**
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* @brief bd71837 sub-driver chip access routines
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*/
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struct bd71837 {
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struct device *dev;
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struct i2c_client *i2c_client;
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struct regmap *regmap;
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struct mutex io_mutex;
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unsigned int id;
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/* IRQ Handling */
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int chip_irq; /**< bd71837 irq to host cpu */
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struct regmap_irq_chip_data *irq_data;
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/* Client devices */
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struct bd71837_pmic *pmic; /**< client device regulator */
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struct bd71837_power *power; /**< client device battery */
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struct bd71837_board *of_plat_data;
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/**< Device node parsed board data */
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};
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static inline int bd71837_chip_id(struct bd71837 *bd71837)
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{
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return bd71837->id;
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}
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/**
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* @brief bd71837_reg_read
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* read single register's value of bd71837
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* @param bd71837 device to read
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* @param reg register address
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* @return register value if success
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* error number if fail
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*/
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static inline int bd71837_reg_read(struct bd71837 *bd71837, u8 reg)
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{
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int r, val;
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r = regmap_read(bd71837->regmap, reg, &val);
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if (r < 0) {
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return r;
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}
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return val;
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}
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/**
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* @brief bd71837_reg_write
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* write single register of bd71837
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* @param bd71837 device to write
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* @param reg register address
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* @param val value to write
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* @retval 0 if success
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* @retval negative error number if fail
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*/
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static inline int bd71837_reg_write(struct bd71837 *bd71837, u8 reg,
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unsigned int val)
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{
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return regmap_write(bd71837->regmap, reg, val);
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}
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/**
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* @brief bd71837_set_bits
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* set bits in one register of bd71837
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* @param bd71837 device to read
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* @param reg register address
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* @param mask mask bits
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* @retval 0 if success
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* @retval negative error number if fail
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*/
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static inline int bd71837_set_bits(struct bd71837 *bd71837, u8 reg, u8 mask)
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{
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return regmap_update_bits(bd71837->regmap, reg, mask, mask);
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}
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/**
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* @brief bd71837_clear_bits
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* clear bits in one register of bd71837
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* @param bd71837 device to read
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* @param reg register address
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* @param mask mask bits
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* @retval 0 if success
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* @retval negative error number if fail
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*/
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static inline int bd71837_clear_bits(struct bd71837 *bd71837, u8 reg,
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u8 mask)
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{
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return regmap_update_bits(bd71837->regmap, reg, mask, 0);
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}
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/**
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* @brief bd71837_update_bits
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* update bits in one register of bd71837
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* @param bd71837 device to read
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* @param reg register address
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* @param mask mask bits
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* @param val value to update
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* @retval 0 if success
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* @retval negative error number if fail
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*/
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static inline int bd71837_update_bits(struct bd71837 *bd71837, u8 reg,
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u8 mask, u8 val)
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{
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return regmap_update_bits(bd71837->regmap, reg, mask, val);
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}
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/**
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* @brief bd71837 platform data type
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*/
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struct bd71837_gpo_plat_data {
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u32 drv; ///< gpo output drv
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int gpio_base; ///< base gpio number in system
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};
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u8 ext_bd71837_reg_read8(u8 reg);
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int ext_bd71837_reg_write8(int reg, u8 val);
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#define BD71837_DBG0 0x0001
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#define BD71837_DBG1 0x0002
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#define BD71837_DBG2 0x0004
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#define BD71837_DBG3 0x0008
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extern unsigned int bd71837_debug_mask;
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#define bd71837_debug(debug, fmt, arg...) do { if (debug & bd71837_debug_mask) printk("BD71837:" fmt, ##arg); } while (0)
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#endif /* __LINUX_MFD_BD71837_H */
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