![Luis R. Rodriguez](/assets/img/avatar_default.png)
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
697 lines
19 KiB
C
697 lines
19 KiB
C
/*
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* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
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* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
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* Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/******************************\
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Hardware Descriptor Functions
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\******************************/
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#include "ath5k.h"
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#include "reg.h"
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#include "debug.h"
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#include "base.h"
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/*
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* TX Descriptors
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*/
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/*
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* Initialize the 2-word tx control descriptor on 5210/5211
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*/
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static int
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ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
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unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
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unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
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unsigned int rtscts_rate, unsigned int rtscts_duration)
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{
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u32 frame_type;
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struct ath5k_hw_2w_tx_ctl *tx_ctl;
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unsigned int frame_len;
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tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
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/*
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* Validate input
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* - Zero retries don't make sense.
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* - A zero rate will put the HW into a mode where it continously sends
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* noise on the channel, so it is important to avoid this.
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*/
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if (unlikely(tx_tries0 == 0)) {
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ATH5K_ERR(ah->ah_sc, "zero retries\n");
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WARN_ON(1);
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return -EINVAL;
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}
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if (unlikely(tx_rate0 == 0)) {
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ATH5K_ERR(ah->ah_sc, "zero rate\n");
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WARN_ON(1);
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return -EINVAL;
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}
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/* Clear descriptor */
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memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
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/* Setup control descriptor */
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/* Verify and set frame length */
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/* remove padding we might have added before */
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frame_len = pkt_len - ath5k_pad_size(hdr_len) + FCS_LEN;
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if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
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return -EINVAL;
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tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
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/* Verify and set buffer length */
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/* NB: beacon's BufLen must be a multiple of 4 bytes */
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if (type == AR5K_PKT_TYPE_BEACON)
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pkt_len = roundup(pkt_len, 4);
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if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
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return -EINVAL;
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tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
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/*
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* Verify and set header length
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* XXX: I only found that on 5210 code, does it work on 5211 ?
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*/
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if (ah->ah_version == AR5K_AR5210) {
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if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
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return -EINVAL;
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tx_ctl->tx_control_0 |=
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AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
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}
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/*Diferences between 5210-5211*/
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if (ah->ah_version == AR5K_AR5210) {
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switch (type) {
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case AR5K_PKT_TYPE_BEACON:
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case AR5K_PKT_TYPE_PROBE_RESP:
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frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
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case AR5K_PKT_TYPE_PIFS:
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frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
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default:
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frame_type = type /*<< 2 ?*/;
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}
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tx_ctl->tx_control_0 |=
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AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
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AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
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} else {
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tx_ctl->tx_control_0 |=
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AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
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AR5K_REG_SM(antenna_mode,
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AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
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tx_ctl->tx_control_1 |=
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AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
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}
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#define _TX_FLAGS(_c, _flag) \
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if (flags & AR5K_TXDESC_##_flag) { \
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tx_ctl->tx_control_##_c |= \
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AR5K_2W_TX_DESC_CTL##_c##_##_flag; \
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}
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_TX_FLAGS(0, CLRDMASK);
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_TX_FLAGS(0, VEOL);
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_TX_FLAGS(0, INTREQ);
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_TX_FLAGS(0, RTSENA);
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_TX_FLAGS(1, NOACK);
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#undef _TX_FLAGS
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/*
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* WEP crap
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*/
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if (key_index != AR5K_TXKEYIX_INVALID) {
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tx_ctl->tx_control_0 |=
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AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
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tx_ctl->tx_control_1 |=
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AR5K_REG_SM(key_index,
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AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
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}
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/*
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* RTS/CTS Duration [5210 ?]
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*/
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if ((ah->ah_version == AR5K_AR5210) &&
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(flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
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tx_ctl->tx_control_1 |= rtscts_duration &
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AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
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return 0;
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}
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/*
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* Initialize the 4-word tx control descriptor on 5212
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*/
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static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
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struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
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enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
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unsigned int tx_tries0, unsigned int key_index,
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unsigned int antenna_mode, unsigned int flags,
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unsigned int rtscts_rate,
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unsigned int rtscts_duration)
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{
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struct ath5k_hw_4w_tx_ctl *tx_ctl;
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unsigned int frame_len;
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ATH5K_TRACE(ah->ah_sc);
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tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
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/*
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* Validate input
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* - Zero retries don't make sense.
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* - A zero rate will put the HW into a mode where it continously sends
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* noise on the channel, so it is important to avoid this.
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*/
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if (unlikely(tx_tries0 == 0)) {
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ATH5K_ERR(ah->ah_sc, "zero retries\n");
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WARN_ON(1);
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return -EINVAL;
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}
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if (unlikely(tx_rate0 == 0)) {
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ATH5K_ERR(ah->ah_sc, "zero rate\n");
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WARN_ON(1);
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return -EINVAL;
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}
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tx_power += ah->ah_txpower.txp_offset;
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if (tx_power > AR5K_TUNE_MAX_TXPOWER)
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tx_power = AR5K_TUNE_MAX_TXPOWER;
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/* Clear descriptor */
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memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
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/* Setup control descriptor */
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/* Verify and set frame length */
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/* remove padding we might have added before */
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frame_len = pkt_len - ath5k_pad_size(hdr_len) + FCS_LEN;
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if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
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return -EINVAL;
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tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
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/* Verify and set buffer length */
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/* NB: beacon's BufLen must be a multiple of 4 bytes */
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if (type == AR5K_PKT_TYPE_BEACON)
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pkt_len = roundup(pkt_len, 4);
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if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
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return -EINVAL;
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tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
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tx_ctl->tx_control_0 |=
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AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
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AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
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tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
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AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
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tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
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tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
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#define _TX_FLAGS(_c, _flag) \
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if (flags & AR5K_TXDESC_##_flag) { \
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tx_ctl->tx_control_##_c |= \
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AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
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}
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_TX_FLAGS(0, CLRDMASK);
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_TX_FLAGS(0, VEOL);
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_TX_FLAGS(0, INTREQ);
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_TX_FLAGS(0, RTSENA);
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_TX_FLAGS(0, CTSENA);
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_TX_FLAGS(1, NOACK);
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#undef _TX_FLAGS
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/*
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* WEP crap
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*/
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if (key_index != AR5K_TXKEYIX_INVALID) {
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tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
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tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
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AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
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}
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/*
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* RTS/CTS
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*/
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if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
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if ((flags & AR5K_TXDESC_RTSENA) &&
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(flags & AR5K_TXDESC_CTSENA))
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return -EINVAL;
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tx_ctl->tx_control_2 |= rtscts_duration &
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AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
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tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
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AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
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}
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return 0;
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}
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/*
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* Initialize a 4-word multi rate retry tx control descriptor on 5212
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*/
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static int
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ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
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u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
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{
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struct ath5k_hw_4w_tx_ctl *tx_ctl;
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/*
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* Rates can be 0 as long as the retry count is 0 too.
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* A zero rate and nonzero retry count will put the HW into a mode where
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* it continously sends noise on the channel, so it is important to
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* avoid this.
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*/
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if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
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(tx_rate2 == 0 && tx_tries2 != 0) ||
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(tx_rate3 == 0 && tx_tries3 != 0))) {
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ATH5K_ERR(ah->ah_sc, "zero rate\n");
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WARN_ON(1);
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return -EINVAL;
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}
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if (ah->ah_version == AR5K_AR5212) {
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tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
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#define _XTX_TRIES(_n) \
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if (tx_tries##_n) { \
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tx_ctl->tx_control_2 |= \
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AR5K_REG_SM(tx_tries##_n, \
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
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tx_ctl->tx_control_3 |= \
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AR5K_REG_SM(tx_rate##_n, \
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
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}
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_XTX_TRIES(1);
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_XTX_TRIES(2);
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_XTX_TRIES(3);
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#undef _XTX_TRIES
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return 1;
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}
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return 0;
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}
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/* no mrr support for cards older than 5212 */
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static int
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ath5k_hw_setup_no_mrr(struct ath5k_hw *ah, struct ath5k_desc *desc,
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unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
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u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
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{
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return 0;
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}
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/*
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* Proccess the tx status descriptor on 5210/5211
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*/
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static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
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struct ath5k_desc *desc, struct ath5k_tx_status *ts)
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{
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struct ath5k_hw_2w_tx_ctl *tx_ctl;
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struct ath5k_hw_tx_status *tx_status;
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ATH5K_TRACE(ah->ah_sc);
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tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
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tx_status = &desc->ud.ds_tx5210.tx_stat;
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/* No frame has been send or error */
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if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
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return -EINPROGRESS;
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/*
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* Get descriptor status
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*/
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ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
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AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
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ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
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AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
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ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
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AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
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/*TODO: ts->ts_virtcol + test*/
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ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_SEQ_NUM);
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ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
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ts->ts_antenna = 1;
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ts->ts_status = 0;
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ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
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AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
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ts->ts_retry[0] = ts->ts_longretry;
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ts->ts_final_idx = 0;
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if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
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if (tx_status->tx_status_0 &
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AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
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ts->ts_status |= AR5K_TXERR_XRETRY;
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if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
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ts->ts_status |= AR5K_TXERR_FIFO;
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if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
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ts->ts_status |= AR5K_TXERR_FILT;
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}
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return 0;
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}
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/*
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* Proccess a tx status descriptor on 5212
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*/
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static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
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struct ath5k_desc *desc, struct ath5k_tx_status *ts)
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{
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struct ath5k_hw_4w_tx_ctl *tx_ctl;
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struct ath5k_hw_tx_status *tx_status;
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ATH5K_TRACE(ah->ah_sc);
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tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
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tx_status = &desc->ud.ds_tx5212.tx_stat;
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/* No frame has been send or error */
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if (unlikely(!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE)))
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return -EINPROGRESS;
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/*
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* Get descriptor status
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*/
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ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
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AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
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ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
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AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
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ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
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AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
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ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_SEQ_NUM);
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ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
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ts->ts_antenna = (tx_status->tx_status_1 &
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AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
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ts->ts_status = 0;
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ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
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/* The longretry counter has the number of un-acked retries
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* for the final rate. To get the total number of retries
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* we have to add the retry counters for the other rates
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* as well
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*/
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ts->ts_retry[ts->ts_final_idx] = ts->ts_longretry;
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switch (ts->ts_final_idx) {
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case 3:
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ts->ts_rate[3] = AR5K_REG_MS(tx_ctl->tx_control_3,
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
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ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
|
|
AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
|
|
ts->ts_longretry += ts->ts_retry[2];
|
|
/* fall through */
|
|
case 2:
|
|
ts->ts_rate[2] = AR5K_REG_MS(tx_ctl->tx_control_3,
|
|
AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
|
|
|
|
ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
|
|
AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
|
|
ts->ts_longretry += ts->ts_retry[1];
|
|
/* fall through */
|
|
case 1:
|
|
ts->ts_rate[1] = AR5K_REG_MS(tx_ctl->tx_control_3,
|
|
AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
|
|
|
|
ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
|
|
AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
|
|
ts->ts_longretry += ts->ts_retry[0];
|
|
/* fall through */
|
|
case 0:
|
|
ts->ts_rate[0] = tx_ctl->tx_control_3 &
|
|
AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
|
|
break;
|
|
}
|
|
|
|
/* TX error */
|
|
if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
|
|
if (tx_status->tx_status_0 &
|
|
AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
|
|
ts->ts_status |= AR5K_TXERR_XRETRY;
|
|
|
|
if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
|
|
ts->ts_status |= AR5K_TXERR_FIFO;
|
|
|
|
if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
|
|
ts->ts_status |= AR5K_TXERR_FILT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* RX Descriptors
|
|
*/
|
|
|
|
/*
|
|
* Initialize an rx control descriptor
|
|
*/
|
|
static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
|
|
u32 size, unsigned int flags)
|
|
{
|
|
struct ath5k_hw_rx_ctl *rx_ctl;
|
|
|
|
ATH5K_TRACE(ah->ah_sc);
|
|
rx_ctl = &desc->ud.ds_rx.rx_ctl;
|
|
|
|
/*
|
|
* Clear the descriptor
|
|
* If we don't clean the status descriptor,
|
|
* while scanning we get too many results,
|
|
* most of them virtual, after some secs
|
|
* of scanning system hangs. M.F.
|
|
*/
|
|
memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
|
|
|
|
/* Setup descriptor */
|
|
rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
|
|
if (unlikely(rx_ctl->rx_control_1 != size))
|
|
return -EINVAL;
|
|
|
|
if (flags & AR5K_RXDESC_INTREQ)
|
|
rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Proccess the rx status descriptor on 5210/5211
|
|
*/
|
|
static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
|
|
struct ath5k_desc *desc, struct ath5k_rx_status *rs)
|
|
{
|
|
struct ath5k_hw_rx_status *rx_status;
|
|
|
|
rx_status = &desc->ud.ds_rx.u.rx_stat;
|
|
|
|
/* No frame received / not ready */
|
|
if (unlikely(!(rx_status->rx_status_1 &
|
|
AR5K_5210_RX_DESC_STATUS1_DONE)))
|
|
return -EINPROGRESS;
|
|
|
|
/*
|
|
* Frame receive status
|
|
*/
|
|
rs->rs_datalen = rx_status->rx_status_0 &
|
|
AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
|
|
rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
|
|
AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
|
|
rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
|
|
AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
|
|
rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
|
|
AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA);
|
|
rs->rs_more = !!(rx_status->rx_status_0 &
|
|
AR5K_5210_RX_DESC_STATUS0_MORE);
|
|
/* TODO: this timestamp is 13 bit, later on we assume 15 bit */
|
|
rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
|
|
AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
|
|
rs->rs_status = 0;
|
|
rs->rs_phyerr = 0;
|
|
|
|
/*
|
|
* Key table status
|
|
*/
|
|
if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
|
|
rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
|
|
AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
|
|
else
|
|
rs->rs_keyix = AR5K_RXKEYIX_INVALID;
|
|
|
|
/*
|
|
* Receive/descriptor errors
|
|
*/
|
|
if (!(rx_status->rx_status_1 &
|
|
AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
|
|
if (rx_status->rx_status_1 &
|
|
AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
|
|
rs->rs_status |= AR5K_RXERR_CRC;
|
|
|
|
if (rx_status->rx_status_1 &
|
|
AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
|
|
rs->rs_status |= AR5K_RXERR_FIFO;
|
|
|
|
if (rx_status->rx_status_1 &
|
|
AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
|
|
rs->rs_status |= AR5K_RXERR_PHY;
|
|
rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
|
|
AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
|
|
}
|
|
|
|
if (rx_status->rx_status_1 &
|
|
AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
|
|
rs->rs_status |= AR5K_RXERR_DECRYPT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Proccess the rx status descriptor on 5212
|
|
*/
|
|
static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
|
|
struct ath5k_desc *desc, struct ath5k_rx_status *rs)
|
|
{
|
|
struct ath5k_hw_rx_status *rx_status;
|
|
struct ath5k_hw_rx_error *rx_err;
|
|
|
|
ATH5K_TRACE(ah->ah_sc);
|
|
rx_status = &desc->ud.ds_rx.u.rx_stat;
|
|
|
|
/* Overlay on error */
|
|
rx_err = &desc->ud.ds_rx.u.rx_err;
|
|
|
|
/* No frame received / not ready */
|
|
if (unlikely(!(rx_status->rx_status_1 &
|
|
AR5K_5212_RX_DESC_STATUS1_DONE)))
|
|
return -EINPROGRESS;
|
|
|
|
/*
|
|
* Frame receive status
|
|
*/
|
|
rs->rs_datalen = rx_status->rx_status_0 &
|
|
AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
|
|
rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
|
|
AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
|
|
rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
|
|
AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
|
|
rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
|
|
AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
|
|
rs->rs_more = !!(rx_status->rx_status_0 &
|
|
AR5K_5212_RX_DESC_STATUS0_MORE);
|
|
rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
|
|
AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
|
|
rs->rs_status = 0;
|
|
rs->rs_phyerr = 0;
|
|
|
|
/*
|
|
* Key table status
|
|
*/
|
|
if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
|
|
rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
|
|
AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
|
|
else
|
|
rs->rs_keyix = AR5K_RXKEYIX_INVALID;
|
|
|
|
/*
|
|
* Receive/descriptor errors
|
|
*/
|
|
if (!(rx_status->rx_status_1 &
|
|
AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
|
|
if (rx_status->rx_status_1 &
|
|
AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
|
|
rs->rs_status |= AR5K_RXERR_CRC;
|
|
|
|
if (rx_status->rx_status_1 &
|
|
AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
|
|
rs->rs_status |= AR5K_RXERR_PHY;
|
|
rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
|
|
AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
|
|
}
|
|
|
|
if (rx_status->rx_status_1 &
|
|
AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
|
|
rs->rs_status |= AR5K_RXERR_DECRYPT;
|
|
|
|
if (rx_status->rx_status_1 &
|
|
AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
|
|
rs->rs_status |= AR5K_RXERR_MIC;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Init function pointers inside ath5k_hw struct
|
|
*/
|
|
int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
|
|
{
|
|
|
|
if (ah->ah_version != AR5K_AR5210 &&
|
|
ah->ah_version != AR5K_AR5211 &&
|
|
ah->ah_version != AR5K_AR5212)
|
|
return -ENOTSUPP;
|
|
|
|
/* XXX: What is this magic value and where is it used ? */
|
|
if (ah->ah_version == AR5K_AR5212)
|
|
ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
|
|
else if (ah->ah_version == AR5K_AR5211)
|
|
ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
|
|
|
|
if (ah->ah_version == AR5K_AR5212) {
|
|
ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
|
|
ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
|
|
ah->ah_setup_mrr_tx_desc = ath5k_hw_setup_mrr_tx_desc;
|
|
ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
|
|
} else {
|
|
ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
|
|
ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
|
|
ah->ah_setup_mrr_tx_desc = ath5k_hw_setup_no_mrr;
|
|
ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
|
|
}
|
|
|
|
if (ah->ah_version == AR5K_AR5212)
|
|
ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
|
|
else if (ah->ah_version <= AR5K_AR5211)
|
|
ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
|
|
|
|
return 0;
|
|
}
|
|
|