![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
380 lines
9 KiB
C
380 lines
9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/percpu.h>
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#include <linux/sched_clock.h>
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#include <linux/time.h>
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#include "timer-of.h"
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#ifdef CONFIG_ARM
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#include <asm/mach/time.h>
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#endif
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#define RTC_SECONDS 0x08
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#define RTC_SHADOW_SECONDS 0x0c
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#define RTC_MILLISECONDS 0x10
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#define TIMERUS_CNTR_1US 0x10
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#define TIMERUS_USEC_CFG 0x14
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#define TIMERUS_CNTR_FREEZE 0x4c
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#define TIMER_PTV 0x0
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#define TIMER_PTV_EN BIT(31)
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#define TIMER_PTV_PER BIT(30)
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#define TIMER_PCR 0x4
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#define TIMER_PCR_INTR_CLR BIT(30)
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#ifdef CONFIG_ARM
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#define TIMER_CPU0 0x50 /* TIMER3 */
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#else
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#define TIMER_CPU0 0x90 /* TIMER10 */
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#define TIMER10_IRQ_IDX 10
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#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu)
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#endif
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#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
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static u32 usec_config;
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static void __iomem *timer_reg_base;
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#ifdef CONFIG_ARM
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static struct delay_timer tegra_delay_timer;
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#endif
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static int tegra_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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void __iomem *reg_base = timer_of_base(to_timer_of(evt));
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writel(TIMER_PTV_EN |
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((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
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reg_base + TIMER_PTV);
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return 0;
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}
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static int tegra_timer_shutdown(struct clock_event_device *evt)
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{
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void __iomem *reg_base = timer_of_base(to_timer_of(evt));
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writel(0, reg_base + TIMER_PTV);
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return 0;
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}
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static int tegra_timer_set_periodic(struct clock_event_device *evt)
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{
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void __iomem *reg_base = timer_of_base(to_timer_of(evt));
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writel(TIMER_PTV_EN | TIMER_PTV_PER |
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((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
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reg_base + TIMER_PTV);
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return 0;
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}
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static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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void __iomem *reg_base = timer_of_base(to_timer_of(evt));
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writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void tegra_timer_suspend(struct clock_event_device *evt)
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{
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void __iomem *reg_base = timer_of_base(to_timer_of(evt));
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writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
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}
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static void tegra_timer_resume(struct clock_event_device *evt)
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{
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writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
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}
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#ifdef CONFIG_ARM64
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static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
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.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
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.clkevt = {
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.name = "tegra_timer",
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.rating = 460,
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.set_next_event = tegra_timer_set_next_event,
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.set_state_shutdown = tegra_timer_shutdown,
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.set_state_periodic = tegra_timer_set_periodic,
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.set_state_oneshot = tegra_timer_shutdown,
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.tick_resume = tegra_timer_shutdown,
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.suspend = tegra_timer_suspend,
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.resume = tegra_timer_resume,
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},
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};
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static int tegra_timer_setup(unsigned int cpu)
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{
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struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
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irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
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enable_irq(to->clkevt.irq);
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clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
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1, /* min */
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0x1fffffff); /* 29 bits */
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return 0;
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}
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static int tegra_timer_stop(unsigned int cpu)
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{
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struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
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to->clkevt.set_state_shutdown(&to->clkevt);
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disable_irq_nosync(to->clkevt.irq);
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return 0;
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}
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#else /* CONFIG_ARM */
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static struct timer_of tegra_to = {
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.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
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.clkevt = {
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.name = "tegra_timer",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_DYNIRQ,
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.set_next_event = tegra_timer_set_next_event,
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.set_state_shutdown = tegra_timer_shutdown,
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.set_state_periodic = tegra_timer_set_periodic,
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.set_state_oneshot = tegra_timer_shutdown,
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.tick_resume = tegra_timer_shutdown,
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.suspend = tegra_timer_suspend,
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.resume = tegra_timer_resume,
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.cpumask = cpu_possible_mask,
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},
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.of_irq = {
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.index = 2,
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.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
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.handler = tegra_timer_isr,
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},
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};
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static u64 notrace tegra_read_sched_clock(void)
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{
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return readl(timer_reg_base + TIMERUS_CNTR_1US);
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}
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static unsigned long tegra_delay_timer_read_counter_long(void)
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{
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return readl(timer_reg_base + TIMERUS_CNTR_1US);
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}
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static struct timer_of suspend_rtc_to = {
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.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
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};
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/*
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* tegra_rtc_read - Reads the Tegra RTC registers
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* Care must be taken that this funciton is not called while the
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* tegra_rtc driver could be executing to avoid race conditions
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* on the RTC shadow register
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*/
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static u64 tegra_rtc_read_ms(struct clocksource *cs)
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{
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u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS);
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u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS);
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return (u64)s * MSEC_PER_SEC + ms;
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}
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static struct clocksource suspend_rtc_clocksource = {
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.name = "tegra_suspend_timer",
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.rating = 200,
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.read = tegra_rtc_read_ms,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
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};
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#endif
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static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
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{
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int ret = 0;
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ret = timer_of_init(np, to);
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if (ret < 0)
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goto out;
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timer_reg_base = timer_of_base(to);
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/*
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* Configure microsecond timers to have 1MHz clock
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* Config register is 0xqqww, where qq is "dividend", ww is "divisor"
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* Uses n+1 scheme
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*/
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switch (timer_of_rate(to)) {
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case 12000000:
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usec_config = 0x000b; /* (11+1)/(0+1) */
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break;
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case 12800000:
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usec_config = 0x043f; /* (63+1)/(4+1) */
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break;
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case 13000000:
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usec_config = 0x000c; /* (12+1)/(0+1) */
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break;
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case 16800000:
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usec_config = 0x0453; /* (83+1)/(4+1) */
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break;
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case 19200000:
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usec_config = 0x045f; /* (95+1)/(4+1) */
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break;
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case 26000000:
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usec_config = 0x0019; /* (25+1)/(0+1) */
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break;
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case 38400000:
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usec_config = 0x04bf; /* (191+1)/(4+1) */
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break;
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case 48000000:
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usec_config = 0x002f; /* (47+1)/(0+1) */
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break;
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default:
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ret = -EINVAL;
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goto out;
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}
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writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
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out:
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return ret;
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}
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#ifdef CONFIG_ARM64
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static int __init tegra_init_timer(struct device_node *np)
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{
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int cpu, ret = 0;
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struct timer_of *to;
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to = this_cpu_ptr(&tegra_to);
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ret = tegra_timer_common_init(np, to);
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if (ret < 0)
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goto out;
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for_each_possible_cpu(cpu) {
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struct timer_of *cpu_to;
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cpu_to = per_cpu_ptr(&tegra_to, cpu);
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cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
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cpu_to->of_clk.rate = timer_of_rate(to);
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cpu_to->clkevt.cpumask = cpumask_of(cpu);
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cpu_to->clkevt.irq =
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irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
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if (!cpu_to->clkevt.irq) {
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pr_err("%s: can't map IRQ for CPU%d\n",
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__func__, cpu);
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ret = -EINVAL;
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goto out;
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}
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irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
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ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
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IRQF_TIMER | IRQF_NOBALANCING,
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cpu_to->clkevt.name, &cpu_to->clkevt);
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if (ret) {
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pr_err("%s: cannot setup irq %d for CPU%d\n",
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__func__, cpu_to->clkevt.irq, cpu);
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ret = -EINVAL;
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goto out_irq;
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}
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}
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cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
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"AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
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tegra_timer_stop);
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return ret;
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out_irq:
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for_each_possible_cpu(cpu) {
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struct timer_of *cpu_to;
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cpu_to = per_cpu_ptr(&tegra_to, cpu);
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if (cpu_to->clkevt.irq) {
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free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
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irq_dispose_mapping(cpu_to->clkevt.irq);
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}
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}
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out:
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timer_of_cleanup(to);
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return ret;
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}
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#else /* CONFIG_ARM */
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static int __init tegra_init_timer(struct device_node *np)
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{
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int ret = 0;
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ret = tegra_timer_common_init(np, &tegra_to);
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if (ret < 0)
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goto out;
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tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
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tegra_to.of_clk.rate = 1000000; /* microsecond timer */
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sched_clock_register(tegra_read_sched_clock, 32,
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timer_of_rate(&tegra_to));
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ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
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"timer_us", timer_of_rate(&tegra_to),
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300, 32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("Failed to register clocksource\n");
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goto out;
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}
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tegra_delay_timer.read_current_timer =
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tegra_delay_timer_read_counter_long;
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tegra_delay_timer.freq = timer_of_rate(&tegra_to);
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register_current_timer_delay(&tegra_delay_timer);
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clockevents_config_and_register(&tegra_to.clkevt,
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timer_of_rate(&tegra_to),
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0x1,
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0x1fffffff);
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return ret;
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out:
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timer_of_cleanup(&tegra_to);
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return ret;
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}
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static int __init tegra20_init_rtc(struct device_node *np)
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{
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int ret;
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ret = timer_of_init(np, &suspend_rtc_to);
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if (ret)
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return ret;
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clocksource_register_hz(&suspend_rtc_clocksource, 1000);
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return 0;
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}
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TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
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#endif
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TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
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TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
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