![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
624 lines
16 KiB
C
624 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 DMAC support
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*/
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include "virt-dma.h"
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#define JZ_DMA_NR_CHANS 6
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#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
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#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
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#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
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#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
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#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
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#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
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#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
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#define JZ_REG_DMA_CTRL 0x300
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#define JZ_REG_DMA_IRQ 0x304
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#define JZ_REG_DMA_DOORBELL 0x308
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#define JZ_REG_DMA_DOORBELL_SET 0x30C
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#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
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#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
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#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
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#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
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#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
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#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
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#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
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#define JZ_DMA_CMD_SRC_INC BIT(23)
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#define JZ_DMA_CMD_DST_INC BIT(22)
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#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
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#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
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#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
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#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
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#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
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#define JZ_DMA_CMD_DESC_VALID BIT(4)
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#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
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#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
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#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
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#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
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#define JZ_DMA_CMD_FLAGS_OFFSET 22
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#define JZ_DMA_CMD_RDIL_OFFSET 16
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#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
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#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
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#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
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#define JZ_DMA_CMD_MODE_OFFSET 7
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#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
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#define JZ_DMA_CTRL_HALT BIT(3)
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#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
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#define JZ_DMA_CTRL_ENABLE BIT(0)
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enum jz4740_dma_width {
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JZ4740_DMA_WIDTH_32BIT = 0,
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JZ4740_DMA_WIDTH_8BIT = 1,
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JZ4740_DMA_WIDTH_16BIT = 2,
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};
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enum jz4740_dma_transfer_size {
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JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
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JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
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JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
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JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
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JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
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};
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enum jz4740_dma_flags {
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JZ4740_DMA_SRC_AUTOINC = 0x2,
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JZ4740_DMA_DST_AUTOINC = 0x1,
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};
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enum jz4740_dma_mode {
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JZ4740_DMA_MODE_SINGLE = 0,
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JZ4740_DMA_MODE_BLOCK = 1,
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};
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struct jz4740_dma_sg {
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dma_addr_t addr;
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unsigned int len;
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};
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struct jz4740_dma_desc {
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struct virt_dma_desc vdesc;
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enum dma_transfer_direction direction;
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bool cyclic;
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unsigned int num_sgs;
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struct jz4740_dma_sg sg[];
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};
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struct jz4740_dmaengine_chan {
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struct virt_dma_chan vchan;
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unsigned int id;
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struct dma_slave_config config;
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dma_addr_t fifo_addr;
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unsigned int transfer_shift;
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struct jz4740_dma_desc *desc;
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unsigned int next_sg;
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};
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struct jz4740_dma_dev {
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struct dma_device ddev;
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void __iomem *base;
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struct clk *clk;
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struct jz4740_dmaengine_chan chan[JZ_DMA_NR_CHANS];
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};
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static struct jz4740_dma_dev *jz4740_dma_chan_get_dev(
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struct jz4740_dmaengine_chan *chan)
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{
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return container_of(chan->vchan.chan.device, struct jz4740_dma_dev,
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ddev);
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}
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static struct jz4740_dmaengine_chan *to_jz4740_dma_chan(struct dma_chan *c)
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{
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return container_of(c, struct jz4740_dmaengine_chan, vchan.chan);
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}
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static struct jz4740_dma_desc *to_jz4740_dma_desc(struct virt_dma_desc *vdesc)
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{
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return container_of(vdesc, struct jz4740_dma_desc, vdesc);
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}
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static inline uint32_t jz4740_dma_read(struct jz4740_dma_dev *dmadev,
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unsigned int reg)
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{
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return readl(dmadev->base + reg);
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}
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static inline void jz4740_dma_write(struct jz4740_dma_dev *dmadev,
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unsigned reg, uint32_t val)
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{
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writel(val, dmadev->base + reg);
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}
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static inline void jz4740_dma_write_mask(struct jz4740_dma_dev *dmadev,
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unsigned int reg, uint32_t val, uint32_t mask)
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{
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uint32_t tmp;
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tmp = jz4740_dma_read(dmadev, reg);
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tmp &= ~mask;
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tmp |= val;
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jz4740_dma_write(dmadev, reg, tmp);
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}
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static struct jz4740_dma_desc *jz4740_dma_alloc_desc(unsigned int num_sgs)
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{
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return kzalloc(sizeof(struct jz4740_dma_desc) +
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sizeof(struct jz4740_dma_sg) * num_sgs, GFP_ATOMIC);
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}
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static enum jz4740_dma_width jz4740_dma_width(enum dma_slave_buswidth width)
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{
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switch (width) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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return JZ4740_DMA_WIDTH_8BIT;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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return JZ4740_DMA_WIDTH_16BIT;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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return JZ4740_DMA_WIDTH_32BIT;
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default:
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return JZ4740_DMA_WIDTH_32BIT;
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}
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}
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static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst)
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{
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if (maxburst <= 1)
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return JZ4740_DMA_TRANSFER_SIZE_1BYTE;
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else if (maxburst <= 3)
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return JZ4740_DMA_TRANSFER_SIZE_2BYTE;
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else if (maxburst <= 15)
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return JZ4740_DMA_TRANSFER_SIZE_4BYTE;
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else if (maxburst <= 31)
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return JZ4740_DMA_TRANSFER_SIZE_16BYTE;
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return JZ4740_DMA_TRANSFER_SIZE_32BYTE;
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}
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static int jz4740_dma_slave_config_write(struct dma_chan *c,
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struct dma_slave_config *config,
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enum dma_transfer_direction direction)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
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enum jz4740_dma_width src_width;
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enum jz4740_dma_width dst_width;
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enum jz4740_dma_transfer_size transfer_size;
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enum jz4740_dma_flags flags;
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uint32_t cmd;
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switch (direction) {
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case DMA_MEM_TO_DEV:
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flags = JZ4740_DMA_SRC_AUTOINC;
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transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
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chan->fifo_addr = config->dst_addr;
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break;
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case DMA_DEV_TO_MEM:
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flags = JZ4740_DMA_DST_AUTOINC;
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transfer_size = jz4740_dma_maxburst(config->src_maxburst);
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chan->fifo_addr = config->src_addr;
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break;
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default:
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return -EINVAL;
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}
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src_width = jz4740_dma_width(config->src_addr_width);
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dst_width = jz4740_dma_width(config->dst_addr_width);
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switch (transfer_size) {
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case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
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chan->transfer_shift = 1;
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break;
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case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
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chan->transfer_shift = 2;
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break;
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case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
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chan->transfer_shift = 4;
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break;
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case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
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chan->transfer_shift = 5;
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break;
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default:
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chan->transfer_shift = 0;
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break;
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}
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cmd = flags << JZ_DMA_CMD_FLAGS_OFFSET;
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cmd |= src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
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cmd |= dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
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cmd |= transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
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cmd |= JZ4740_DMA_MODE_SINGLE << JZ_DMA_CMD_MODE_OFFSET;
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cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
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jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
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jz4740_dma_write(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0);
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jz4740_dma_write(dmadev, JZ_REG_DMA_REQ_TYPE(chan->id),
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config->slave_id);
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return 0;
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}
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static int jz4740_dma_slave_config(struct dma_chan *c,
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struct dma_slave_config *config)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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memcpy(&chan->config, config, sizeof(*config));
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return 0;
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}
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static int jz4740_dma_terminate_all(struct dma_chan *c)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&chan->vchan.lock, flags);
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jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
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JZ_DMA_STATUS_CTRL_ENABLE);
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chan->desc = NULL;
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vchan_get_all_descriptors(&chan->vchan, &head);
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spin_unlock_irqrestore(&chan->vchan.lock, flags);
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vchan_dma_desc_free_list(&chan->vchan, &head);
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return 0;
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}
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static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan *chan)
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{
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struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
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dma_addr_t src_addr, dst_addr;
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struct virt_dma_desc *vdesc;
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struct jz4740_dma_sg *sg;
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jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
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JZ_DMA_STATUS_CTRL_ENABLE);
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if (!chan->desc) {
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vdesc = vchan_next_desc(&chan->vchan);
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if (!vdesc)
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return 0;
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chan->desc = to_jz4740_dma_desc(vdesc);
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chan->next_sg = 0;
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}
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if (chan->next_sg == chan->desc->num_sgs)
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chan->next_sg = 0;
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sg = &chan->desc->sg[chan->next_sg];
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if (chan->desc->direction == DMA_MEM_TO_DEV) {
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src_addr = sg->addr;
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dst_addr = chan->fifo_addr;
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} else {
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src_addr = chan->fifo_addr;
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dst_addr = sg->addr;
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}
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jz4740_dma_write(dmadev, JZ_REG_DMA_SRC_ADDR(chan->id), src_addr);
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jz4740_dma_write(dmadev, JZ_REG_DMA_DST_ADDR(chan->id), dst_addr);
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jz4740_dma_write(dmadev, JZ_REG_DMA_TRANSFER_COUNT(chan->id),
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sg->len >> chan->transfer_shift);
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chan->next_sg++;
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jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id),
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JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
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JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
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JZ_DMA_STATUS_CTRL_ENABLE);
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jz4740_dma_write_mask(dmadev, JZ_REG_DMA_CTRL,
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JZ_DMA_CTRL_ENABLE,
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JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
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return 0;
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}
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static void jz4740_dma_chan_irq(struct jz4740_dmaengine_chan *chan)
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{
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spin_lock(&chan->vchan.lock);
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if (chan->desc) {
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if (chan->desc->cyclic) {
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vchan_cyclic_callback(&chan->desc->vdesc);
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} else {
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if (chan->next_sg == chan->desc->num_sgs) {
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list_del(&chan->desc->vdesc.node);
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vchan_cookie_complete(&chan->desc->vdesc);
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chan->desc = NULL;
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}
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}
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}
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jz4740_dma_start_transfer(chan);
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spin_unlock(&chan->vchan.lock);
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}
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static irqreturn_t jz4740_dma_irq(int irq, void *devid)
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{
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struct jz4740_dma_dev *dmadev = devid;
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uint32_t irq_status;
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unsigned int i;
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irq_status = readl(dmadev->base + JZ_REG_DMA_IRQ);
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for (i = 0; i < 6; ++i) {
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if (irq_status & (1 << i)) {
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jz4740_dma_write_mask(dmadev,
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JZ_REG_DMA_STATUS_CTRL(i), 0,
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JZ_DMA_STATUS_CTRL_ENABLE |
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JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
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jz4740_dma_chan_irq(&dmadev->chan[i]);
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}
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}
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return IRQ_HANDLED;
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}
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static void jz4740_dma_issue_pending(struct dma_chan *c)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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unsigned long flags;
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spin_lock_irqsave(&chan->vchan.lock, flags);
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if (vchan_issue_pending(&chan->vchan) && !chan->desc)
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jz4740_dma_start_transfer(chan);
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spin_unlock_irqrestore(&chan->vchan.lock, flags);
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}
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static struct dma_async_tx_descriptor *jz4740_dma_prep_slave_sg(
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struct dma_chan *c, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct jz4740_dma_desc *desc;
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struct scatterlist *sg;
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unsigned int i;
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desc = jz4740_dma_alloc_desc(sg_len);
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if (!desc)
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return NULL;
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for_each_sg(sgl, sg, sg_len, i) {
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desc->sg[i].addr = sg_dma_address(sg);
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desc->sg[i].len = sg_dma_len(sg);
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}
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desc->num_sgs = sg_len;
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desc->direction = direction;
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desc->cyclic = false;
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jz4740_dma_slave_config_write(c, &chan->config, direction);
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
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}
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static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic(
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struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
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size_t period_len, enum dma_transfer_direction direction,
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unsigned long flags)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct jz4740_dma_desc *desc;
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unsigned int num_periods, i;
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if (buf_len % period_len)
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return NULL;
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num_periods = buf_len / period_len;
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desc = jz4740_dma_alloc_desc(num_periods);
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if (!desc)
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return NULL;
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for (i = 0; i < num_periods; i++) {
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desc->sg[i].addr = buf_addr;
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desc->sg[i].len = period_len;
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buf_addr += period_len;
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}
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desc->num_sgs = num_periods;
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desc->direction = direction;
|
|
desc->cyclic = true;
|
|
|
|
jz4740_dma_slave_config_write(c, &chan->config, direction);
|
|
|
|
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
|
|
}
|
|
|
|
static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
|
|
struct jz4740_dma_desc *desc, unsigned int next_sg)
|
|
{
|
|
struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
|
|
unsigned int residue, count;
|
|
unsigned int i;
|
|
|
|
residue = 0;
|
|
|
|
for (i = next_sg; i < desc->num_sgs; i++)
|
|
residue += desc->sg[i].len;
|
|
|
|
if (next_sg != 0) {
|
|
count = jz4740_dma_read(dmadev,
|
|
JZ_REG_DMA_TRANSFER_COUNT(chan->id));
|
|
residue += count << chan->transfer_shift;
|
|
}
|
|
|
|
return residue;
|
|
}
|
|
|
|
static enum dma_status jz4740_dma_tx_status(struct dma_chan *c,
|
|
dma_cookie_t cookie, struct dma_tx_state *state)
|
|
{
|
|
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
|
|
struct virt_dma_desc *vdesc;
|
|
enum dma_status status;
|
|
unsigned long flags;
|
|
|
|
status = dma_cookie_status(c, cookie, state);
|
|
if (status == DMA_COMPLETE || !state)
|
|
return status;
|
|
|
|
spin_lock_irqsave(&chan->vchan.lock, flags);
|
|
vdesc = vchan_find_desc(&chan->vchan, cookie);
|
|
if (cookie == chan->desc->vdesc.tx.cookie) {
|
|
state->residue = jz4740_dma_desc_residue(chan, chan->desc,
|
|
chan->next_sg);
|
|
} else if (vdesc) {
|
|
state->residue = jz4740_dma_desc_residue(chan,
|
|
to_jz4740_dma_desc(vdesc), 0);
|
|
} else {
|
|
state->residue = 0;
|
|
}
|
|
spin_unlock_irqrestore(&chan->vchan.lock, flags);
|
|
|
|
return status;
|
|
}
|
|
|
|
static void jz4740_dma_free_chan_resources(struct dma_chan *c)
|
|
{
|
|
vchan_free_chan_resources(to_virt_chan(c));
|
|
}
|
|
|
|
static void jz4740_dma_desc_free(struct virt_dma_desc *vdesc)
|
|
{
|
|
kfree(container_of(vdesc, struct jz4740_dma_desc, vdesc));
|
|
}
|
|
|
|
#define JZ4740_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
|
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
|
|
|
|
static int jz4740_dma_probe(struct platform_device *pdev)
|
|
{
|
|
struct jz4740_dmaengine_chan *chan;
|
|
struct jz4740_dma_dev *dmadev;
|
|
struct dma_device *dd;
|
|
unsigned int i;
|
|
struct resource *res;
|
|
int ret;
|
|
int irq;
|
|
|
|
dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
|
|
if (!dmadev)
|
|
return -EINVAL;
|
|
|
|
dd = &dmadev->ddev;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
dmadev->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(dmadev->base))
|
|
return PTR_ERR(dmadev->base);
|
|
|
|
dmadev->clk = clk_get(&pdev->dev, "dma");
|
|
if (IS_ERR(dmadev->clk))
|
|
return PTR_ERR(dmadev->clk);
|
|
|
|
clk_prepare_enable(dmadev->clk);
|
|
|
|
dma_cap_set(DMA_SLAVE, dd->cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, dd->cap_mask);
|
|
dd->device_free_chan_resources = jz4740_dma_free_chan_resources;
|
|
dd->device_tx_status = jz4740_dma_tx_status;
|
|
dd->device_issue_pending = jz4740_dma_issue_pending;
|
|
dd->device_prep_slave_sg = jz4740_dma_prep_slave_sg;
|
|
dd->device_prep_dma_cyclic = jz4740_dma_prep_dma_cyclic;
|
|
dd->device_config = jz4740_dma_slave_config;
|
|
dd->device_terminate_all = jz4740_dma_terminate_all;
|
|
dd->src_addr_widths = JZ4740_DMA_BUSWIDTHS;
|
|
dd->dst_addr_widths = JZ4740_DMA_BUSWIDTHS;
|
|
dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
|
dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
|
|
dd->dev = &pdev->dev;
|
|
INIT_LIST_HEAD(&dd->channels);
|
|
|
|
for (i = 0; i < JZ_DMA_NR_CHANS; i++) {
|
|
chan = &dmadev->chan[i];
|
|
chan->id = i;
|
|
chan->vchan.desc_free = jz4740_dma_desc_free;
|
|
vchan_init(&chan->vchan, dd);
|
|
}
|
|
|
|
ret = dma_async_device_register(dd);
|
|
if (ret)
|
|
goto err_clk;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
ret = request_irq(irq, jz4740_dma_irq, 0, dev_name(&pdev->dev), dmadev);
|
|
if (ret)
|
|
goto err_unregister;
|
|
|
|
platform_set_drvdata(pdev, dmadev);
|
|
|
|
return 0;
|
|
|
|
err_unregister:
|
|
dma_async_device_unregister(dd);
|
|
err_clk:
|
|
clk_disable_unprepare(dmadev->clk);
|
|
return ret;
|
|
}
|
|
|
|
static void jz4740_cleanup_vchan(struct dma_device *dmadev)
|
|
{
|
|
struct jz4740_dmaengine_chan *chan, *_chan;
|
|
|
|
list_for_each_entry_safe(chan, _chan,
|
|
&dmadev->channels, vchan.chan.device_node) {
|
|
list_del(&chan->vchan.chan.device_node);
|
|
tasklet_kill(&chan->vchan.task);
|
|
}
|
|
}
|
|
|
|
|
|
static int jz4740_dma_remove(struct platform_device *pdev)
|
|
{
|
|
struct jz4740_dma_dev *dmadev = platform_get_drvdata(pdev);
|
|
int irq = platform_get_irq(pdev, 0);
|
|
|
|
free_irq(irq, dmadev);
|
|
|
|
jz4740_cleanup_vchan(&dmadev->ddev);
|
|
dma_async_device_unregister(&dmadev->ddev);
|
|
clk_disable_unprepare(dmadev->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver jz4740_dma_driver = {
|
|
.probe = jz4740_dma_probe,
|
|
.remove = jz4740_dma_remove,
|
|
.driver = {
|
|
.name = "jz4740-dma",
|
|
},
|
|
};
|
|
module_platform_driver(jz4740_dma_driver);
|
|
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("JZ4740 DMA driver");
|
|
MODULE_LICENSE("GPL v2");
|