![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
487 lines
11 KiB
C
487 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
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*
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* 2013 (c) Aeroflex Gaisler AB
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*
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* This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
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* IP core library.
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*
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* Full documentation of the GRGPIO core can be found here:
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* http://www.gaisler.com/products/grlib/grip.pdf
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*
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* See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
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* information on open firmware properties.
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*
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* Contributors: Andreas Larsson <andreas@gaisler.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/gpio/driver.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/bitops.h>
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#define GRGPIO_MAX_NGPIO 32
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#define GRGPIO_DATA 0x00
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#define GRGPIO_OUTPUT 0x04
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#define GRGPIO_DIR 0x08
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#define GRGPIO_IMASK 0x0c
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#define GRGPIO_IPOL 0x10
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#define GRGPIO_IEDGE 0x14
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#define GRGPIO_BYPASS 0x18
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#define GRGPIO_IMAP_BASE 0x20
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/* Structure for an irq of the core - called an underlying irq */
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struct grgpio_uirq {
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u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
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u8 uirq; /* Underlying irq of the gpio driver */
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};
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/*
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* Structure for an irq of a gpio line handed out by this driver. The index is
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* used to map to the corresponding underlying irq.
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*/
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struct grgpio_lirq {
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s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
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u8 irq; /* irq for the gpio line */
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};
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struct grgpio_priv {
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struct gpio_chip gc;
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void __iomem *regs;
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struct device *dev;
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u32 imask; /* irq mask shadow register */
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/*
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* The grgpio core can have multiple "underlying" irqs. The gpio lines
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* can be mapped to any one or none of these underlying irqs
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* independently of each other. This driver sets up an irq domain and
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* hands out separate irqs to each gpio line
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*/
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struct irq_domain *domain;
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/*
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* This array contains information on each underlying irq, each
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* irq of the grgpio core itself.
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*/
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struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
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/*
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* This array contains information for each gpio line on the irqs
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* obtains from this driver. An index value of -1 for a certain gpio
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* line indicates that the line has no irq. Otherwise the index connects
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* the irq to the underlying irq by pointing into the uirqs array.
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*/
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struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
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};
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static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
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int val)
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{
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struct gpio_chip *gc = &priv->gc;
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if (val)
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priv->imask |= BIT(offset);
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else
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priv->imask &= ~BIT(offset);
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gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
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}
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static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct grgpio_priv *priv = gpiochip_get_data(gc);
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if (offset >= gc->ngpio)
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return -ENXIO;
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if (priv->lirqs[offset].index < 0)
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return -ENXIO;
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return irq_create_mapping(priv->domain, offset);
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}
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/* -------------------- IRQ chip functions -------------------- */
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static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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u32 mask = BIT(d->hwirq);
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u32 ipol;
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u32 iedge;
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u32 pol;
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u32 edge;
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switch (type) {
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case IRQ_TYPE_LEVEL_LOW:
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pol = 0;
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edge = 0;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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pol = mask;
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edge = 0;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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pol = 0;
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edge = mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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pol = mask;
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edge = mask;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
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iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
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priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
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priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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return 0;
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}
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static void grgpio_irq_mask(struct irq_data *d)
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{
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struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
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int offset = d->hwirq;
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unsigned long flags;
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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grgpio_set_imask(priv, offset, 0);
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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}
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static void grgpio_irq_unmask(struct irq_data *d)
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{
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struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
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int offset = d->hwirq;
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unsigned long flags;
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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grgpio_set_imask(priv, offset, 1);
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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}
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static struct irq_chip grgpio_irq_chip = {
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.name = "grgpio",
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.irq_mask = grgpio_irq_mask,
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.irq_unmask = grgpio_irq_unmask,
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.irq_set_type = grgpio_irq_set_type,
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};
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static irqreturn_t grgpio_irq_handler(int irq, void *dev)
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{
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struct grgpio_priv *priv = dev;
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int ngpio = priv->gc.ngpio;
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unsigned long flags;
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int i;
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int match = 0;
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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/*
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* For each gpio line, call its interrupt handler if it its underlying
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* irq matches the current irq that is handled.
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*/
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for (i = 0; i < ngpio; i++) {
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struct grgpio_lirq *lirq = &priv->lirqs[i];
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if (priv->imask & BIT(i) && lirq->index >= 0 &&
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priv->uirqs[lirq->index].uirq == irq) {
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generic_handle_irq(lirq->irq);
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match = 1;
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}
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}
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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if (!match)
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dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
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return IRQ_HANDLED;
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}
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/*
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* This function will be called as a consequence of the call to
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* irq_create_mapping in grgpio_to_irq
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*/
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static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct grgpio_priv *priv = d->host_data;
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struct grgpio_lirq *lirq;
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struct grgpio_uirq *uirq;
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unsigned long flags;
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int offset = hwirq;
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int ret = 0;
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if (!priv)
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return -EINVAL;
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lirq = &priv->lirqs[offset];
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if (lirq->index < 0)
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return -EINVAL;
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dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
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irq, offset);
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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/* Request underlying irq if not already requested */
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lirq->irq = irq;
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uirq = &priv->uirqs[lirq->index];
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if (uirq->refcnt == 0) {
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ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
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dev_name(priv->dev), priv);
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if (ret) {
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dev_err(priv->dev,
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"Could not request underlying irq %d\n",
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uirq->uirq);
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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return ret;
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}
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}
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uirq->refcnt++;
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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/* Setup irq */
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irq_set_chip_data(irq, priv);
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irq_set_chip_and_handler(irq, &grgpio_irq_chip,
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handle_simple_irq);
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irq_set_noprobe(irq);
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return ret;
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}
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static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
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{
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struct grgpio_priv *priv = d->host_data;
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int index;
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struct grgpio_lirq *lirq;
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struct grgpio_uirq *uirq;
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unsigned long flags;
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int ngpio = priv->gc.ngpio;
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int i;
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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/* Free underlying irq if last user unmapped */
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index = -1;
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for (i = 0; i < ngpio; i++) {
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lirq = &priv->lirqs[i];
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if (lirq->irq == irq) {
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grgpio_set_imask(priv, i, 0);
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lirq->irq = 0;
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index = lirq->index;
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break;
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}
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}
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WARN_ON(index < 0);
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if (index >= 0) {
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uirq = &priv->uirqs[lirq->index];
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uirq->refcnt--;
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if (uirq->refcnt == 0)
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free_irq(uirq->uirq, priv);
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}
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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}
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static const struct irq_domain_ops grgpio_irq_domain_ops = {
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.map = grgpio_irq_map,
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.unmap = grgpio_irq_unmap,
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};
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/* ------------------------------------------------------------ */
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static int grgpio_probe(struct platform_device *ofdev)
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{
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struct device_node *np = ofdev->dev.of_node;
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void __iomem *regs;
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struct gpio_chip *gc;
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struct grgpio_priv *priv;
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struct resource *res;
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int err;
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u32 prop;
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s32 *irqmap;
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int size;
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int i;
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priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(&ofdev->dev, res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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gc = &priv->gc;
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err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
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regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
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BGPIOF_BIG_ENDIAN_BYTE_ORDER);
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if (err) {
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dev_err(&ofdev->dev, "bgpio_init() failed\n");
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return err;
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}
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priv->regs = regs;
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priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
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priv->dev = &ofdev->dev;
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gc->of_node = np;
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gc->owner = THIS_MODULE;
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gc->to_irq = grgpio_to_irq;
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gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
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gc->base = -1;
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err = of_property_read_u32(np, "nbits", &prop);
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if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
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gc->ngpio = GRGPIO_MAX_NGPIO;
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dev_dbg(&ofdev->dev,
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"No or invalid nbits property: assume %d\n", gc->ngpio);
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} else {
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gc->ngpio = prop;
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}
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/*
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* The irqmap contains the index values indicating which underlying irq,
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* if anyone, is connected to that line
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*/
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irqmap = (s32 *)of_get_property(np, "irqmap", &size);
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if (irqmap) {
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if (size < gc->ngpio) {
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dev_err(&ofdev->dev,
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"irqmap shorter than ngpio (%d < %d)\n",
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size, gc->ngpio);
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return -EINVAL;
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}
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priv->domain = irq_domain_add_linear(np, gc->ngpio,
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&grgpio_irq_domain_ops,
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priv);
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if (!priv->domain) {
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dev_err(&ofdev->dev, "Could not add irq domain\n");
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return -EINVAL;
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}
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for (i = 0; i < gc->ngpio; i++) {
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struct grgpio_lirq *lirq;
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int ret;
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lirq = &priv->lirqs[i];
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lirq->index = irqmap[i];
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if (lirq->index < 0)
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continue;
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ret = platform_get_irq(ofdev, lirq->index);
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if (ret <= 0) {
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/*
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* Continue without irq functionality for that
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* gpio line
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*/
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dev_err(priv->dev,
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"Failed to get irq for offset %d\n", i);
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continue;
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}
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priv->uirqs[lirq->index].uirq = ret;
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}
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}
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platform_set_drvdata(ofdev, priv);
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err = gpiochip_add_data(gc, priv);
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if (err) {
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dev_err(&ofdev->dev, "Could not add gpiochip\n");
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if (priv->domain)
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irq_domain_remove(priv->domain);
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return err;
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}
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dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
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priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
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return 0;
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}
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static int grgpio_remove(struct platform_device *ofdev)
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{
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struct grgpio_priv *priv = platform_get_drvdata(ofdev);
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unsigned long flags;
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int i;
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int ret = 0;
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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if (priv->domain) {
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for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
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if (priv->uirqs[i].refcnt != 0) {
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ret = -EBUSY;
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goto out;
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}
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}
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}
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gpiochip_remove(&priv->gc);
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if (priv->domain)
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irq_domain_remove(priv->domain);
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out:
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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return ret;
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}
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static const struct of_device_id grgpio_match[] = {
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{.name = "GAISLER_GPIO"},
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{.name = "01_01a"},
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{},
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};
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MODULE_DEVICE_TABLE(of, grgpio_match);
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static struct platform_driver grgpio_driver = {
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.driver = {
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.name = "grgpio",
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.of_match_table = grgpio_match,
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},
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.probe = grgpio_probe,
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.remove = grgpio_remove,
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};
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module_platform_driver(grgpio_driver);
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MODULE_AUTHOR("Aeroflex Gaisler AB.");
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MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
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MODULE_LICENSE("GPL");
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