![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 1 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.665915326@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
396 lines
11 KiB
C
396 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Xilinx gpio driver for xps/axi_gpio IP.
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*
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* Copyright 2008 - 2013 Xilinx, Inc.
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*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/io.h>
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#include <linux/gpio/driver.h>
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#include <linux/slab.h>
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/* Register Offset Definitions */
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#define XGPIO_DATA_OFFSET (0x0) /* Data register */
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#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
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#define XGPIO_CHANNEL_OFFSET 0x8
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/* Read/Write access to the GPIO registers */
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#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
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# define xgpio_readreg(offset) readl(offset)
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# define xgpio_writereg(offset, val) writel(val, offset)
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#else
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# define xgpio_readreg(offset) __raw_readl(offset)
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# define xgpio_writereg(offset, val) __raw_writel(val, offset)
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#endif
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/**
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* struct xgpio_instance - Stores information about GPIO device
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* @mmchip: OF GPIO chip for memory mapped banks
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* @gpio_width: GPIO width for every channel
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* @gpio_state: GPIO state shadow register
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* @gpio_dir: GPIO direction shadow register
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* @gpio_lock: Lock used for synchronization
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*/
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struct xgpio_instance {
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struct of_mm_gpio_chip mmchip;
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unsigned int gpio_width[2];
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u32 gpio_state[2];
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u32 gpio_dir[2];
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spinlock_t gpio_lock[2];
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};
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static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
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{
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if (gpio >= chip->gpio_width[0])
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return 1;
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return 0;
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}
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static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
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{
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if (xgpio_index(chip, gpio))
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return XGPIO_CHANNEL_OFFSET;
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return 0;
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}
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static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
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{
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if (xgpio_index(chip, gpio))
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return gpio - chip->gpio_width[0];
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return gpio;
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}
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/**
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* xgpio_get - Read the specified signal of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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* This function reads the specified signal of the GPIO device.
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*
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* Return:
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* 0 if direction of GPIO signals is set as input otherwise it
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* returns negative error value.
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*/
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static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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u32 val;
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val = xgpio_readreg(mm_gc->regs + XGPIO_DATA_OFFSET +
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xgpio_regoffset(chip, gpio));
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return !!(val & BIT(xgpio_offset(chip, gpio)));
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}
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/**
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* xgpio_set - Write the specified signal of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* This function writes the specified value in to the specified signal of the
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* GPIO device.
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*/
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static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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/* Write to GPIO signal and set its direction to output */
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if (val)
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chip->gpio_state[index] |= BIT(offset);
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else
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chip->gpio_state[index] &= ~BIT(offset);
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xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET +
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xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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}
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/**
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* xgpio_set_multiple - Write the specified signals of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @mask: Mask of the GPIOS to modify.
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* @bits: Value to be wrote on each GPIO
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*
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* This function writes the specified values into the specified signals of the
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* GPIO devices.
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*/
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static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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unsigned long flags;
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, 0);
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int offset, i;
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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/* Write to GPIO signals */
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for (i = 0; i < gc->ngpio; i++) {
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if (*mask == 0)
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break;
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if (index != xgpio_index(chip, i)) {
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xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET +
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xgpio_regoffset(chip, i),
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chip->gpio_state[index]);
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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index = xgpio_index(chip, i);
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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}
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if (__test_and_clear_bit(i, mask)) {
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offset = xgpio_offset(chip, i);
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if (test_bit(i, bits))
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chip->gpio_state[index] |= BIT(offset);
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else
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chip->gpio_state[index] &= ~BIT(offset);
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}
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}
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xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET +
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xgpio_regoffset(chip, i), chip->gpio_state[index]);
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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}
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/**
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* xgpio_dir_in - Set the direction of the specified GPIO signal as input.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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* Return:
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* 0 - if direction of GPIO signals is set as input
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* otherwise it returns negative error value.
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*/
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static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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unsigned long flags;
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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/* Set the GPIO bit in shadow register and set direction as input */
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chip->gpio_dir[index] |= BIT(offset);
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xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET +
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xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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return 0;
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}
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/**
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* xgpio_dir_out - Set the direction of the specified GPIO signal as output.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* This function sets the direction of specified GPIO signal as output.
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*
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* Return:
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* If all GPIO signals of GPIO chip is configured as input then it returns
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* error otherwise it returns 0.
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*/
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static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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/* Write state of GPIO signal */
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if (val)
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chip->gpio_state[index] |= BIT(offset);
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else
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chip->gpio_state[index] &= ~BIT(offset);
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xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET +
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xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
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/* Clear the GPIO bit in shadow register and set direction as output */
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chip->gpio_dir[index] &= ~BIT(offset);
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xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET +
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xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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return 0;
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}
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/**
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* xgpio_save_regs - Set initial values of GPIO pins
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* @mm_gc: Pointer to memory mapped GPIO chip structure
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*/
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static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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{
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]);
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xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);
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if (!chip->gpio_width[1])
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return;
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xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
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chip->gpio_state[1]);
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xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
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chip->gpio_dir[1]);
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}
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/**
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* xgpio_remove - Remove method for the GPIO device.
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* @pdev: pointer to the platform device
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*
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* This function remove gpiochips and frees all the allocated resources.
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*
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* Return: 0 always
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*/
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static int xgpio_remove(struct platform_device *pdev)
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{
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struct xgpio_instance *chip = platform_get_drvdata(pdev);
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of_mm_gpiochip_remove(&chip->mmchip);
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return 0;
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}
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/**
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* xgpio_of_probe - Probe method for the GPIO device.
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* @pdev: pointer to the platform device
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*
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* Return:
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* It returns 0, if the driver is bound to the GPIO device, or
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* a negative value if there is an error.
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*/
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static int xgpio_probe(struct platform_device *pdev)
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{
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struct xgpio_instance *chip;
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int status = 0;
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struct device_node *np = pdev->dev.of_node;
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u32 is_dual;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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platform_set_drvdata(pdev, chip);
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/* Update GPIO state shadow register with default value */
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of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);
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/* Update GPIO direction shadow register with default value */
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if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
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chip->gpio_dir[0] = 0xFFFFFFFF;
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/*
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* Check device node and parent device node for device width
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* and assume default width of 32
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*/
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if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
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chip->gpio_width[0] = 32;
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spin_lock_init(&chip->gpio_lock[0]);
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if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
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is_dual = 0;
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if (is_dual) {
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/* Update GPIO state shadow register with default value */
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of_property_read_u32(np, "xlnx,dout-default-2",
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&chip->gpio_state[1]);
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/* Update GPIO direction shadow register with default value */
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if (of_property_read_u32(np, "xlnx,tri-default-2",
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&chip->gpio_dir[1]))
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chip->gpio_dir[1] = 0xFFFFFFFF;
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/*
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* Check device node and parent device node for device width
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* and assume default width of 32
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*/
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if (of_property_read_u32(np, "xlnx,gpio2-width",
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&chip->gpio_width[1]))
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chip->gpio_width[1] = 32;
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spin_lock_init(&chip->gpio_lock[1]);
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}
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chip->mmchip.gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
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chip->mmchip.gc.parent = &pdev->dev;
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chip->mmchip.gc.direction_input = xgpio_dir_in;
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chip->mmchip.gc.direction_output = xgpio_dir_out;
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chip->mmchip.gc.get = xgpio_get;
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chip->mmchip.gc.set = xgpio_set;
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chip->mmchip.gc.set_multiple = xgpio_set_multiple;
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chip->mmchip.save_regs = xgpio_save_regs;
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/* Call the OF gpio helper to setup and register the GPIO device */
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status = of_mm_gpiochip_add_data(np, &chip->mmchip, chip);
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if (status) {
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pr_err("%pOF: error in probe function with status %d\n",
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np, status);
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return status;
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}
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return 0;
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}
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static const struct of_device_id xgpio_of_match[] = {
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{ .compatible = "xlnx,xps-gpio-1.00.a", },
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{ /* end of list */ },
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};
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MODULE_DEVICE_TABLE(of, xgpio_of_match);
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static struct platform_driver xgpio_plat_driver = {
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.probe = xgpio_probe,
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.remove = xgpio_remove,
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.driver = {
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.name = "gpio-xilinx",
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.of_match_table = xgpio_of_match,
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},
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};
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static int __init xgpio_init(void)
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{
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return platform_driver_register(&xgpio_plat_driver);
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}
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subsys_initcall(xgpio_init);
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static void __exit xgpio_exit(void)
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{
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platform_driver_unregister(&xgpio_plat_driver);
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}
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module_exit(xgpio_exit);
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MODULE_AUTHOR("Xilinx, Inc.");
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MODULE_DESCRIPTION("Xilinx GPIO driver");
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MODULE_LICENSE("GPL");
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