d08d42de64
ARM Mali midgard GPU is similar to standard 64-bit stage 1 page tables, but have a few differences. Add a new format type to represent the format. The input address size is 48-bits and the output address size is 40-bits (and possibly less?). Note that the later bifrost GPUs follow the standard 64-bit stage 1 format. The differences in the format compared to 64-bit stage 1 format are: The 3rd level page entry bits are 0x1 instead of 0x3 for page entries. The access flags are not read-only and unprivileged, but read and write. This is similar to stage 2 entries, but the memory attributes field matches stage 1 being an index. The nG bit is not set by the vendor driver. This one didn't seem to matter, but we'll keep it aligned to the vendor driver. Cc: Will Deacon <will.deacon@arm.com> Acked-by: Robin Murphy <robin.murphy@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: iommu@lists.linux-foundation.org Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190409205427.6943-2-robh@kernel.org
82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
/*
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* Generic page table allocator for IOMMUs.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright (C) 2014 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#include <linux/bug.h>
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#include <linux/io-pgtable.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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static const struct io_pgtable_init_fns *
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io_pgtable_init_table[IO_PGTABLE_NUM_FMTS] = {
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#ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE
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[ARM_32_LPAE_S1] = &io_pgtable_arm_32_lpae_s1_init_fns,
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[ARM_32_LPAE_S2] = &io_pgtable_arm_32_lpae_s2_init_fns,
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[ARM_64_LPAE_S1] = &io_pgtable_arm_64_lpae_s1_init_fns,
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[ARM_64_LPAE_S2] = &io_pgtable_arm_64_lpae_s2_init_fns,
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[ARM_MALI_LPAE] = &io_pgtable_arm_mali_lpae_init_fns,
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#endif
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#ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S
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[ARM_V7S] = &io_pgtable_arm_v7s_init_fns,
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#endif
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};
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struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,
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struct io_pgtable_cfg *cfg,
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void *cookie)
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{
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struct io_pgtable *iop;
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const struct io_pgtable_init_fns *fns;
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if (fmt >= IO_PGTABLE_NUM_FMTS)
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return NULL;
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fns = io_pgtable_init_table[fmt];
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if (!fns)
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return NULL;
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iop = fns->alloc(cfg, cookie);
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if (!iop)
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return NULL;
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iop->fmt = fmt;
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iop->cookie = cookie;
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iop->cfg = *cfg;
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return &iop->ops;
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}
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EXPORT_SYMBOL_GPL(alloc_io_pgtable_ops);
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/*
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* It is the IOMMU driver's responsibility to ensure that the page table
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* is no longer accessible to the walker by this point.
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*/
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void free_io_pgtable_ops(struct io_pgtable_ops *ops)
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{
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struct io_pgtable *iop;
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if (!ops)
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return;
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iop = container_of(ops, struct io_pgtable, ops);
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io_pgtable_tlb_flush_all(iop);
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io_pgtable_init_table[iop->fmt]->free(iop);
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}
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EXPORT_SYMBOL_GPL(free_io_pgtable_ops);
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