![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
709 lines
18 KiB
C
709 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* IOMMU API for MTK architected m4u v1 implementations
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*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Honghui Zhang <honghui.zhang@mediatek.com>
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*
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* Based on driver/iommu/mtk_iommu.c
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*/
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#include <linux/memblock.h>
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#include <linux/bug.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-iommu.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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#include <linux/of_address.h>
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#include <linux/of_iommu.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/barrier.h>
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#include <asm/dma-iommu.h>
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#include <linux/init.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <soc/mediatek/smi.h>
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#include "mtk_iommu.h"
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#define REG_MMU_PT_BASE_ADDR 0x000
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#define F_ALL_INVLD 0x2
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#define F_MMU_INV_RANGE 0x1
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#define F_INVLD_EN0 BIT(0)
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#define F_INVLD_EN1 BIT(1)
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#define F_MMU_FAULT_VA_MSK 0xfffff000
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#define MTK_PROTECT_PA_ALIGN 128
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#define REG_MMU_CTRL_REG 0x210
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#define F_MMU_CTRL_COHERENT_EN BIT(8)
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#define REG_MMU_IVRP_PADDR 0x214
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#define REG_MMU_INT_CONTROL 0x220
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#define F_INT_TRANSLATION_FAULT BIT(0)
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#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
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#define F_INT_INVALID_PA_FAULT BIT(2)
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#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
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#define F_INT_TABLE_WALK_FAULT BIT(4)
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#define F_INT_TLB_MISS_FAULT BIT(5)
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#define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6)
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#define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7)
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#define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
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#define F_INT_CLR_BIT BIT(12)
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#define REG_MMU_FAULT_ST 0x224
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#define REG_MMU_FAULT_VA 0x228
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#define REG_MMU_INVLD_PA 0x22C
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#define REG_MMU_INT_ID 0x388
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#define REG_MMU_INVALIDATE 0x5c0
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#define REG_MMU_INVLD_START_A 0x5c4
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#define REG_MMU_INVLD_END_A 0x5c8
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#define REG_MMU_INV_SEL 0x5d8
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#define REG_MMU_STANDARD_AXI_MODE 0x5e8
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#define REG_MMU_DCM 0x5f0
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#define F_MMU_DCM_ON BIT(1)
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#define REG_MMU_CPE_DONE 0x60c
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#define F_DESC_VALID 0x2
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#define F_DESC_NONSEC BIT(3)
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#define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
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#define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF)
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/* MTK generation one iommu HW only support 4K size mapping */
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#define MT2701_IOMMU_PAGE_SHIFT 12
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#define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT)
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/*
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* MTK m4u support 4GB iova address space, and only support 4K page
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* mapping. So the pagetable size should be exactly as 4M.
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*/
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#define M2701_IOMMU_PGT_SIZE SZ_4M
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struct mtk_iommu_domain {
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spinlock_t pgtlock; /* lock for page table */
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struct iommu_domain domain;
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u32 *pgt_va;
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dma_addr_t pgt_pa;
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struct mtk_iommu_data *data;
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};
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static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
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{
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return container_of(dom, struct mtk_iommu_domain, domain);
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}
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static const int mt2701_m4u_in_larb[] = {
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LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
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LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
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};
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static inline int mt2701_m4u_to_larb(int id)
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{
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int i;
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for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
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if ((id) >= mt2701_m4u_in_larb[i])
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return i;
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return 0;
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}
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static inline int mt2701_m4u_to_port(int id)
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{
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int larb = mt2701_m4u_to_larb(id);
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return id - mt2701_m4u_in_larb[larb];
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}
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static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
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{
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
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data->base + REG_MMU_INV_SEL);
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writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
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wmb(); /* Make sure the tlb flush all done */
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}
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static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
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unsigned long iova, size_t size)
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{
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int ret;
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u32 tmp;
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
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data->base + REG_MMU_INV_SEL);
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writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
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data->base + REG_MMU_INVLD_START_A);
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writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
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data->base + REG_MMU_INVLD_END_A);
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writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
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ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
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tmp, tmp != 0, 10, 100000);
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if (ret) {
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dev_warn(data->dev,
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"Partial TLB flush timed out, falling back to full flush\n");
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mtk_iommu_tlb_flush_all(data);
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}
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/* Clear the CPE status */
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writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
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}
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static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
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{
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struct mtk_iommu_data *data = dev_id;
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struct mtk_iommu_domain *dom = data->m4u_dom;
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u32 int_state, regval, fault_iova, fault_pa;
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unsigned int fault_larb, fault_port;
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/* Read error information from registers */
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int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
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fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
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fault_iova &= F_MMU_FAULT_VA_MSK;
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fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
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regval = readl_relaxed(data->base + REG_MMU_INT_ID);
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fault_larb = MT2701_M4U_TF_LARB(regval);
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fault_port = MT2701_M4U_TF_PORT(regval);
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/*
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* MTK v1 iommu HW could not determine whether the fault is read or
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* write fault, report as read fault.
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*/
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if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
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IOMMU_FAULT_READ))
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dev_err_ratelimited(data->dev,
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"fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
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int_state, fault_iova, fault_pa,
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fault_larb, fault_port);
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/* Interrupt clear */
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regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
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regval |= F_INT_CLR_BIT;
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writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
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mtk_iommu_tlb_flush_all(data);
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return IRQ_HANDLED;
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}
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static void mtk_iommu_config(struct mtk_iommu_data *data,
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struct device *dev, bool enable)
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{
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struct mtk_smi_larb_iommu *larb_mmu;
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unsigned int larbid, portid;
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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int i;
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for (i = 0; i < fwspec->num_ids; ++i) {
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larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
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portid = mt2701_m4u_to_port(fwspec->ids[i]);
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larb_mmu = &data->smi_imu.larb_imu[larbid];
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dev_dbg(dev, "%s iommu port: %d\n",
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enable ? "enable" : "disable", portid);
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if (enable)
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larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
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else
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larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
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}
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}
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static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
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{
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struct mtk_iommu_domain *dom = data->m4u_dom;
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spin_lock_init(&dom->pgtlock);
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dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
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&dom->pgt_pa, GFP_KERNEL);
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if (!dom->pgt_va)
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return -ENOMEM;
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writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
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dom->data = data;
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return 0;
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}
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static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
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{
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struct mtk_iommu_domain *dom;
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if (type != IOMMU_DOMAIN_UNMANAGED)
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return NULL;
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dom = kzalloc(sizeof(*dom), GFP_KERNEL);
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if (!dom)
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return NULL;
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return &dom->domain;
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}
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static void mtk_iommu_domain_free(struct iommu_domain *domain)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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struct mtk_iommu_data *data = dom->data;
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dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
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dom->pgt_va, dom->pgt_pa);
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kfree(to_mtk_domain(domain));
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}
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static int mtk_iommu_attach_device(struct iommu_domain *domain,
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struct device *dev)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
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int ret;
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if (!data)
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return -ENODEV;
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if (!data->m4u_dom) {
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data->m4u_dom = dom;
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ret = mtk_iommu_domain_finalise(data);
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if (ret) {
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data->m4u_dom = NULL;
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return ret;
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}
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}
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mtk_iommu_config(data, dev, true);
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return 0;
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}
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static void mtk_iommu_detach_device(struct iommu_domain *domain,
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struct device *dev)
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{
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struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
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if (!data)
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return;
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mtk_iommu_config(data, dev, false);
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}
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static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
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unsigned long flags;
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unsigned int i;
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u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
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u32 pabase = (u32)paddr;
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int map_size = 0;
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spin_lock_irqsave(&dom->pgtlock, flags);
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for (i = 0; i < page_num; i++) {
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if (pgt_base_iova[i]) {
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memset(pgt_base_iova, 0, i * sizeof(u32));
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break;
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}
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pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
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pabase += MT2701_IOMMU_PAGE_SIZE;
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map_size += MT2701_IOMMU_PAGE_SIZE;
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}
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spin_unlock_irqrestore(&dom->pgtlock, flags);
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mtk_iommu_tlb_flush_range(dom->data, iova, size);
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return map_size == size ? 0 : -EEXIST;
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}
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static size_t mtk_iommu_unmap(struct iommu_domain *domain,
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unsigned long iova, size_t size)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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unsigned long flags;
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u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
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unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
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spin_lock_irqsave(&dom->pgtlock, flags);
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memset(pgt_base_iova, 0, page_num * sizeof(u32));
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spin_unlock_irqrestore(&dom->pgtlock, flags);
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mtk_iommu_tlb_flush_range(dom->data, iova, size);
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return size;
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}
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static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
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dma_addr_t iova)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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unsigned long flags;
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phys_addr_t pa;
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spin_lock_irqsave(&dom->pgtlock, flags);
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pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
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pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
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spin_unlock_irqrestore(&dom->pgtlock, flags);
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return pa;
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}
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static const struct iommu_ops mtk_iommu_ops;
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/*
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* MTK generation one iommu HW only support one iommu domain, and all the client
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* sharing the same iova address space.
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*/
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static int mtk_iommu_create_mapping(struct device *dev,
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struct of_phandle_args *args)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct mtk_iommu_data *data;
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struct platform_device *m4updev;
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struct dma_iommu_mapping *mtk_mapping;
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struct device *m4udev;
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int ret;
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if (args->args_count != 1) {
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dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
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args->args_count);
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return -EINVAL;
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}
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if (!fwspec) {
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ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops);
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if (ret)
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return ret;
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fwspec = dev_iommu_fwspec_get(dev);
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} else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
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return -EINVAL;
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}
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if (!fwspec->iommu_priv) {
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/* Get the m4u device */
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m4updev = of_find_device_by_node(args->np);
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if (WARN_ON(!m4updev))
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return -EINVAL;
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fwspec->iommu_priv = platform_get_drvdata(m4updev);
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}
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ret = iommu_fwspec_add_ids(dev, args->args, 1);
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if (ret)
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return ret;
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data = fwspec->iommu_priv;
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m4udev = data->dev;
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mtk_mapping = m4udev->archdata.iommu;
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if (!mtk_mapping) {
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/* MTK iommu support 4GB iova address space. */
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mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
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0, 1ULL << 32);
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if (IS_ERR(mtk_mapping))
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return PTR_ERR(mtk_mapping);
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m4udev->archdata.iommu = mtk_mapping;
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}
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return 0;
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}
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static int mtk_iommu_add_device(struct device *dev)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct dma_iommu_mapping *mtk_mapping;
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struct of_phandle_args iommu_spec;
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struct of_phandle_iterator it;
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struct mtk_iommu_data *data;
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struct iommu_group *group;
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int err;
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of_for_each_phandle(&it, err, dev->of_node, "iommus",
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"#iommu-cells", 0) {
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int count = of_phandle_iterator_args(&it, iommu_spec.args,
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MAX_PHANDLE_ARGS);
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iommu_spec.np = of_node_get(it.node);
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iommu_spec.args_count = count;
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mtk_iommu_create_mapping(dev, &iommu_spec);
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/* dev->iommu_fwspec might have changed */
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fwspec = dev_iommu_fwspec_get(dev);
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of_node_put(iommu_spec.np);
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}
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|
if (!fwspec || fwspec->ops != &mtk_iommu_ops)
|
|
return -ENODEV; /* Not a iommu client device */
|
|
|
|
/*
|
|
* This is a short-term bodge because the ARM DMA code doesn't
|
|
* understand multi-device groups, but we have to call into it
|
|
* successfully (and not just rely on a normal IOMMU API attach
|
|
* here) in order to set the correct DMA API ops on @dev.
|
|
*/
|
|
group = iommu_group_alloc();
|
|
if (IS_ERR(group))
|
|
return PTR_ERR(group);
|
|
|
|
err = iommu_group_add_device(group, dev);
|
|
iommu_group_put(group);
|
|
if (err)
|
|
return err;
|
|
|
|
data = fwspec->iommu_priv;
|
|
mtk_mapping = data->dev->archdata.iommu;
|
|
err = arm_iommu_attach_device(dev, mtk_mapping);
|
|
if (err) {
|
|
iommu_group_remove_device(dev);
|
|
return err;
|
|
}
|
|
|
|
return iommu_device_link(&data->iommu, dev);
|
|
}
|
|
|
|
static void mtk_iommu_remove_device(struct device *dev)
|
|
{
|
|
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
|
|
struct mtk_iommu_data *data;
|
|
|
|
if (!fwspec || fwspec->ops != &mtk_iommu_ops)
|
|
return;
|
|
|
|
data = fwspec->iommu_priv;
|
|
iommu_device_unlink(&data->iommu, dev);
|
|
|
|
iommu_group_remove_device(dev);
|
|
iommu_fwspec_free(dev);
|
|
}
|
|
|
|
static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
|
|
{
|
|
u32 regval;
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(data->bclk);
|
|
if (ret) {
|
|
dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
|
|
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
|
|
|
|
regval = F_INT_TRANSLATION_FAULT |
|
|
F_INT_MAIN_MULTI_HIT_FAULT |
|
|
F_INT_INVALID_PA_FAULT |
|
|
F_INT_ENTRY_REPLACEMENT_FAULT |
|
|
F_INT_TABLE_WALK_FAULT |
|
|
F_INT_TLB_MISS_FAULT |
|
|
F_INT_PFH_DMA_FIFO_OVERFLOW |
|
|
F_INT_MISS_DMA_FIFO_OVERFLOW;
|
|
writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
|
|
|
|
/* protect memory,hw will write here while translation fault */
|
|
writel_relaxed(data->protect_base,
|
|
data->base + REG_MMU_IVRP_PADDR);
|
|
|
|
writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
|
|
|
|
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
|
|
dev_name(data->dev), (void *)data)) {
|
|
writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
|
|
clk_disable_unprepare(data->bclk);
|
|
dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct iommu_ops mtk_iommu_ops = {
|
|
.domain_alloc = mtk_iommu_domain_alloc,
|
|
.domain_free = mtk_iommu_domain_free,
|
|
.attach_dev = mtk_iommu_attach_device,
|
|
.detach_dev = mtk_iommu_detach_device,
|
|
.map = mtk_iommu_map,
|
|
.unmap = mtk_iommu_unmap,
|
|
.iova_to_phys = mtk_iommu_iova_to_phys,
|
|
.add_device = mtk_iommu_add_device,
|
|
.remove_device = mtk_iommu_remove_device,
|
|
.pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT,
|
|
};
|
|
|
|
static const struct of_device_id mtk_iommu_of_ids[] = {
|
|
{ .compatible = "mediatek,mt2701-m4u", },
|
|
{}
|
|
};
|
|
|
|
static const struct component_master_ops mtk_iommu_com_ops = {
|
|
.bind = mtk_iommu_bind,
|
|
.unbind = mtk_iommu_unbind,
|
|
};
|
|
|
|
static int mtk_iommu_probe(struct platform_device *pdev)
|
|
{
|
|
struct mtk_iommu_data *data;
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *res;
|
|
struct component_match *match = NULL;
|
|
struct of_phandle_args larb_spec;
|
|
struct of_phandle_iterator it;
|
|
void *protect;
|
|
int larb_nr, ret, err;
|
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
data->dev = dev;
|
|
|
|
/* Protect memory. HW will access here while translation fault.*/
|
|
protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
|
|
GFP_KERNEL | GFP_DMA);
|
|
if (!protect)
|
|
return -ENOMEM;
|
|
data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
data->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(data->base))
|
|
return PTR_ERR(data->base);
|
|
|
|
data->irq = platform_get_irq(pdev, 0);
|
|
if (data->irq < 0)
|
|
return data->irq;
|
|
|
|
data->bclk = devm_clk_get(dev, "bclk");
|
|
if (IS_ERR(data->bclk))
|
|
return PTR_ERR(data->bclk);
|
|
|
|
larb_nr = 0;
|
|
of_for_each_phandle(&it, err, dev->of_node,
|
|
"mediatek,larbs", NULL, 0) {
|
|
struct platform_device *plarbdev;
|
|
int count = of_phandle_iterator_args(&it, larb_spec.args,
|
|
MAX_PHANDLE_ARGS);
|
|
|
|
if (count)
|
|
continue;
|
|
|
|
larb_spec.np = of_node_get(it.node);
|
|
if (!of_device_is_available(larb_spec.np))
|
|
continue;
|
|
|
|
plarbdev = of_find_device_by_node(larb_spec.np);
|
|
if (!plarbdev) {
|
|
plarbdev = of_platform_device_create(
|
|
larb_spec.np, NULL,
|
|
platform_bus_type.dev_root);
|
|
if (!plarbdev) {
|
|
of_node_put(larb_spec.np);
|
|
return -EPROBE_DEFER;
|
|
}
|
|
}
|
|
|
|
data->smi_imu.larb_imu[larb_nr].dev = &plarbdev->dev;
|
|
component_match_add_release(dev, &match, release_of,
|
|
compare_of, larb_spec.np);
|
|
larb_nr++;
|
|
}
|
|
|
|
data->smi_imu.larb_nr = larb_nr;
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
ret = mtk_iommu_hw_init(data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
|
|
dev_name(&pdev->dev));
|
|
if (ret)
|
|
return ret;
|
|
|
|
iommu_device_set_ops(&data->iommu, &mtk_iommu_ops);
|
|
|
|
ret = iommu_device_register(&data->iommu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!iommu_present(&platform_bus_type))
|
|
bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
|
|
|
|
return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
|
|
}
|
|
|
|
static int mtk_iommu_remove(struct platform_device *pdev)
|
|
{
|
|
struct mtk_iommu_data *data = platform_get_drvdata(pdev);
|
|
|
|
iommu_device_sysfs_remove(&data->iommu);
|
|
iommu_device_unregister(&data->iommu);
|
|
|
|
if (iommu_present(&platform_bus_type))
|
|
bus_set_iommu(&platform_bus_type, NULL);
|
|
|
|
clk_disable_unprepare(data->bclk);
|
|
devm_free_irq(&pdev->dev, data->irq, data);
|
|
component_master_del(&pdev->dev, &mtk_iommu_com_ops);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mtk_iommu_suspend(struct device *dev)
|
|
{
|
|
struct mtk_iommu_data *data = dev_get_drvdata(dev);
|
|
struct mtk_iommu_suspend_reg *reg = &data->reg;
|
|
void __iomem *base = data->base;
|
|
|
|
reg->standard_axi_mode = readl_relaxed(base +
|
|
REG_MMU_STANDARD_AXI_MODE);
|
|
reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
|
|
reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
|
|
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mtk_iommu_resume(struct device *dev)
|
|
{
|
|
struct mtk_iommu_data *data = dev_get_drvdata(dev);
|
|
struct mtk_iommu_suspend_reg *reg = &data->reg;
|
|
void __iomem *base = data->base;
|
|
|
|
writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
|
|
writel_relaxed(reg->standard_axi_mode,
|
|
base + REG_MMU_STANDARD_AXI_MODE);
|
|
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
|
|
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
|
|
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
|
|
writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops mtk_iommu_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
|
|
};
|
|
|
|
static struct platform_driver mtk_iommu_driver = {
|
|
.probe = mtk_iommu_probe,
|
|
.remove = mtk_iommu_remove,
|
|
.driver = {
|
|
.name = "mtk-iommu-v1",
|
|
.of_match_table = mtk_iommu_of_ids,
|
|
.pm = &mtk_iommu_pm_ops,
|
|
}
|
|
};
|
|
|
|
static int __init m4u_init(void)
|
|
{
|
|
return platform_driver_register(&mtk_iommu_driver);
|
|
}
|
|
subsys_initcall(m4u_init);
|