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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin st fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 111 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.567572064@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
387 lines
9 KiB
C
387 lines
9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* IOMMU API for Graphics Address Relocation Table on Tegra20
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*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Hiroshi DOYU <hdoyu@nvidia.com>
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*/
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#define dev_fmt(fmt) "gart: " fmt
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/vmalloc.h>
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#include <soc/tegra/mc.h>
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#define GART_REG_BASE 0x24
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#define GART_CONFIG (0x24 - GART_REG_BASE)
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#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
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#define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
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#define GART_ENTRY_PHYS_ADDR_VALID BIT(31)
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#define GART_PAGE_SHIFT 12
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#define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT)
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#define GART_PAGE_MASK GENMASK(30, GART_PAGE_SHIFT)
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/* bitmap of the page sizes currently supported */
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#define GART_IOMMU_PGSIZES (GART_PAGE_SIZE)
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struct gart_device {
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void __iomem *regs;
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u32 *savedata;
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unsigned long iovmm_base; /* offset to vmm_area start */
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unsigned long iovmm_end; /* offset to vmm_area end */
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spinlock_t pte_lock; /* for pagetable */
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spinlock_t dom_lock; /* for active domain */
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unsigned int active_devices; /* number of active devices */
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struct iommu_domain *active_domain; /* current active domain */
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struct iommu_device iommu; /* IOMMU Core handle */
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struct device *dev;
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};
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static struct gart_device *gart_handle; /* unique for a system */
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static bool gart_debug;
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/*
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* Any interaction between any block on PPSB and a block on APB or AHB
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* must have these read-back to ensure the APB/AHB bus transaction is
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* complete before initiating activity on the PPSB block.
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*/
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#define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG)
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#define for_each_gart_pte(gart, iova) \
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for (iova = gart->iovmm_base; \
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iova < gart->iovmm_end; \
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iova += GART_PAGE_SIZE)
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static inline void gart_set_pte(struct gart_device *gart,
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unsigned long iova, unsigned long pte)
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{
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writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR);
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writel_relaxed(pte, gart->regs + GART_ENTRY_DATA);
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}
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static inline unsigned long gart_read_pte(struct gart_device *gart,
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unsigned long iova)
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{
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unsigned long pte;
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writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR);
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pte = readl_relaxed(gart->regs + GART_ENTRY_DATA);
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return pte;
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}
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static void do_gart_setup(struct gart_device *gart, const u32 *data)
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{
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unsigned long iova;
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for_each_gart_pte(gart, iova)
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gart_set_pte(gart, iova, data ? *(data++) : 0);
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writel_relaxed(1, gart->regs + GART_CONFIG);
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FLUSH_GART_REGS(gart);
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}
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static inline bool gart_iova_range_invalid(struct gart_device *gart,
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unsigned long iova, size_t bytes)
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{
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return unlikely(iova < gart->iovmm_base || bytes != GART_PAGE_SIZE ||
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iova + bytes > gart->iovmm_end);
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}
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static inline bool gart_pte_valid(struct gart_device *gart, unsigned long iova)
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{
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return !!(gart_read_pte(gart, iova) & GART_ENTRY_PHYS_ADDR_VALID);
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}
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static int gart_iommu_attach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct gart_device *gart = gart_handle;
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int ret = 0;
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spin_lock(&gart->dom_lock);
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if (gart->active_domain && gart->active_domain != domain) {
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ret = -EBUSY;
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} else if (dev->archdata.iommu != domain) {
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dev->archdata.iommu = domain;
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gart->active_domain = domain;
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gart->active_devices++;
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}
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spin_unlock(&gart->dom_lock);
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return ret;
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}
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static void gart_iommu_detach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct gart_device *gart = gart_handle;
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spin_lock(&gart->dom_lock);
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if (dev->archdata.iommu == domain) {
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dev->archdata.iommu = NULL;
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if (--gart->active_devices == 0)
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gart->active_domain = NULL;
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}
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spin_unlock(&gart->dom_lock);
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}
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static struct iommu_domain *gart_iommu_domain_alloc(unsigned type)
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{
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struct iommu_domain *domain;
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if (type != IOMMU_DOMAIN_UNMANAGED)
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return NULL;
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domain = kzalloc(sizeof(*domain), GFP_KERNEL);
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if (domain) {
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domain->geometry.aperture_start = gart_handle->iovmm_base;
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domain->geometry.aperture_end = gart_handle->iovmm_end - 1;
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domain->geometry.force_aperture = true;
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}
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return domain;
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}
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static void gart_iommu_domain_free(struct iommu_domain *domain)
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{
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WARN_ON(gart_handle->active_domain == domain);
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kfree(domain);
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}
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static inline int __gart_iommu_map(struct gart_device *gart, unsigned long iova,
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unsigned long pa)
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{
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if (unlikely(gart_debug && gart_pte_valid(gart, iova))) {
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dev_err(gart->dev, "Page entry is in-use\n");
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return -EINVAL;
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}
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gart_set_pte(gart, iova, GART_ENTRY_PHYS_ADDR_VALID | pa);
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return 0;
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}
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static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t pa, size_t bytes, int prot)
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{
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struct gart_device *gart = gart_handle;
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int ret;
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if (gart_iova_range_invalid(gart, iova, bytes))
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return -EINVAL;
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spin_lock(&gart->pte_lock);
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ret = __gart_iommu_map(gart, iova, (unsigned long)pa);
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spin_unlock(&gart->pte_lock);
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return ret;
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}
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static inline int __gart_iommu_unmap(struct gart_device *gart,
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unsigned long iova)
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{
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if (unlikely(gart_debug && !gart_pte_valid(gart, iova))) {
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dev_err(gart->dev, "Page entry is invalid\n");
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return -EINVAL;
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}
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gart_set_pte(gart, iova, 0);
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return 0;
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}
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static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
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size_t bytes)
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{
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struct gart_device *gart = gart_handle;
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int err;
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if (gart_iova_range_invalid(gart, iova, bytes))
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return 0;
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spin_lock(&gart->pte_lock);
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err = __gart_iommu_unmap(gart, iova);
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spin_unlock(&gart->pte_lock);
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return err ? 0 : bytes;
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}
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static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
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dma_addr_t iova)
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{
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struct gart_device *gart = gart_handle;
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unsigned long pte;
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if (gart_iova_range_invalid(gart, iova, GART_PAGE_SIZE))
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return -EINVAL;
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spin_lock(&gart->pte_lock);
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pte = gart_read_pte(gart, iova);
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spin_unlock(&gart->pte_lock);
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return pte & GART_PAGE_MASK;
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}
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static bool gart_iommu_capable(enum iommu_cap cap)
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{
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return false;
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}
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static int gart_iommu_add_device(struct device *dev)
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{
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struct iommu_group *group;
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if (!dev->iommu_fwspec)
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return -ENODEV;
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group = iommu_group_get_for_dev(dev);
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if (IS_ERR(group))
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return PTR_ERR(group);
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iommu_group_put(group);
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iommu_device_link(&gart_handle->iommu, dev);
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return 0;
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}
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static void gart_iommu_remove_device(struct device *dev)
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{
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iommu_group_remove_device(dev);
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iommu_device_unlink(&gart_handle->iommu, dev);
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}
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static int gart_iommu_of_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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return 0;
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}
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static void gart_iommu_sync(struct iommu_domain *domain)
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{
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FLUSH_GART_REGS(gart_handle);
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}
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static const struct iommu_ops gart_iommu_ops = {
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.capable = gart_iommu_capable,
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.domain_alloc = gart_iommu_domain_alloc,
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.domain_free = gart_iommu_domain_free,
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.attach_dev = gart_iommu_attach_dev,
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.detach_dev = gart_iommu_detach_dev,
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.add_device = gart_iommu_add_device,
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.remove_device = gart_iommu_remove_device,
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.device_group = generic_device_group,
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.map = gart_iommu_map,
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.unmap = gart_iommu_unmap,
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.iova_to_phys = gart_iommu_iova_to_phys,
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.pgsize_bitmap = GART_IOMMU_PGSIZES,
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.of_xlate = gart_iommu_of_xlate,
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.iotlb_sync_map = gart_iommu_sync,
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.iotlb_sync = gart_iommu_sync,
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};
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int tegra_gart_suspend(struct gart_device *gart)
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{
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u32 *data = gart->savedata;
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unsigned long iova;
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/*
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* All GART users shall be suspended at this point. Disable
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* address translation to trap all GART accesses as invalid
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* memory accesses.
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*/
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writel_relaxed(0, gart->regs + GART_CONFIG);
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FLUSH_GART_REGS(gart);
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for_each_gart_pte(gart, iova)
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*(data++) = gart_read_pte(gart, iova);
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return 0;
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}
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int tegra_gart_resume(struct gart_device *gart)
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{
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do_gart_setup(gart, gart->savedata);
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return 0;
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}
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struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
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{
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struct gart_device *gart;
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struct resource *res;
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int err;
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BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
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/* the GART memory aperture is required */
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res = platform_get_resource(to_platform_device(dev), IORESOURCE_MEM, 1);
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if (!res) {
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dev_err(dev, "Memory aperture resource unavailable\n");
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return ERR_PTR(-ENXIO);
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}
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gart = kzalloc(sizeof(*gart), GFP_KERNEL);
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if (!gart)
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return ERR_PTR(-ENOMEM);
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gart_handle = gart;
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gart->dev = dev;
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gart->regs = mc->regs + GART_REG_BASE;
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gart->iovmm_base = res->start;
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gart->iovmm_end = res->end + 1;
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spin_lock_init(&gart->pte_lock);
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spin_lock_init(&gart->dom_lock);
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do_gart_setup(gart, NULL);
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err = iommu_device_sysfs_add(&gart->iommu, dev, NULL, "gart");
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if (err)
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goto free_gart;
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iommu_device_set_ops(&gart->iommu, &gart_iommu_ops);
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iommu_device_set_fwnode(&gart->iommu, dev->fwnode);
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err = iommu_device_register(&gart->iommu);
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if (err)
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goto remove_sysfs;
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gart->savedata = vmalloc(resource_size(res) / GART_PAGE_SIZE *
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sizeof(u32));
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if (!gart->savedata) {
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err = -ENOMEM;
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goto unregister_iommu;
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}
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return gart;
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unregister_iommu:
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iommu_device_unregister(&gart->iommu);
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remove_sysfs:
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iommu_device_sysfs_remove(&gart->iommu);
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free_gart:
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kfree(gart);
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return ERR_PTR(err);
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}
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module_param(gart_debug, bool, 0644);
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MODULE_PARM_DESC(gart_debug, "Enable GART debugging");
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