b920de1b77
Add architecture support for the MN10300/AM33 CPUs produced by MEI to the kernel. This patch also adds board support for the ASB2303 with the ASB2308 daughter board, and the ASB2305. The only processor supported is the MN103E010, which is an AM33v2 core plus on-chip devices. [akpm@linux-foundation.org: nuke cvs control strings] Signed-off-by: Masakazu Urade <urade.masakazu@jp.panasonic.com> Signed-off-by: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
55 lines
2 KiB
C
55 lines
2 KiB
C
/* MN10300 cache management registers
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_CACHE_H
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#define _ASM_CACHE_H
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#include <asm/cpu-regs.h>
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#include <asm/proc/cache.h>
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#ifndef __ASSEMBLY__
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#define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES)
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#else
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#define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES
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#endif
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/* data cache purge registers
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* - read from the register to unconditionally purge that cache line
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* - write address & 0xffffff00 to conditionally purge that cache line
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* - clear LSB to request invalidation as well
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*/
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#define DCACHE_PURGE(WAY, ENTRY) \
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__SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \
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(ENTRY) * L1_CACHE_BYTES, u32)
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#define DCACHE_PURGE_WAY0(ENTRY) \
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__SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
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#define DCACHE_PURGE_WAY1(ENTRY) \
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__SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
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#define DCACHE_PURGE_WAY2(ENTRY) \
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__SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
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#define DCACHE_PURGE_WAY3(ENTRY) \
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__SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
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/* instruction cache access registers */
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#define ICACHE_DATA(WAY, ENTRY, OFF) \
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__SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
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#define ICACHE_TAG(WAY, ENTRY) \
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__SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
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/* instruction cache access registers */
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#define DCACHE_DATA(WAY, ENTRY, OFF) \
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__SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
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#define DCACHE_TAG(WAY, ENTRY) \
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__SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
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#endif /* _ASM_CACHE_H */
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