1ec7032ad5
Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: Thierry Reding <treding@nvidia.com>
25 lines
863 B
Makefile
25 lines
863 B
Makefile
obj-y += clk.o
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obj-y += clk-audio-sync.o
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obj-y += clk-dfll.o
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obj-y += clk-divider.o
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obj-y += clk-periph.o
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obj-y += clk-periph-fixed.o
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obj-y += clk-periph-gate.o
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obj-y += clk-pll.o
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obj-y += clk-pll-out.o
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obj-y += clk-super.o
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obj-y += clk-tegra-audio.o
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obj-y += clk-tegra-periph.o
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obj-y += clk-tegra-pmc.o
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obj-y += clk-tegra-fixed.o
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obj-y += clk-tegra-super-gen4.o
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obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o
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obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
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obj-y += cvb.o
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obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
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