14866543ad
This tidies up a lot of the PIO/MMIO split. No in-tree platforms were making use of the MMIO overloading through the machvec (nor have any of them been in some time), so we just kill all of that off. The ISA I/O routine wrapping remains unaffected, which remains the only special casing outside of the iomap API that boards need to think about. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
299 lines
9.7 KiB
C
299 lines
9.7 KiB
C
#ifndef __ASM_SH_IO_H
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#define __ASM_SH_IO_H
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/*
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* Convention:
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* read{b,w,l,q}/write{b,w,l,q} are for PCI,
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* while in{b,w,l}/out{b,w,l} are for ISA
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*
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* In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
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* and 'string' versions: ins{b,w,l}/outs{b,w,l}
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*
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* While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
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* automatically, there are also __raw versions, which do not.
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*
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* Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for
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* SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
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* these have the same semantics as the __raw variants, and as such, all
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* new code should be using the __raw versions.
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*
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* All ISA I/O routines are wrapped through the machine vector. If a
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* board does not provide overrides, a generic set that are copied in
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* from the default machine vector are used instead. These are largely
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* for old compat code for I/O offseting to SuperIOs, all of which are
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* better handled through the machvec ioport mapping routines these days.
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*/
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#include <asm/cache.h>
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#include <asm/system.h>
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#include <asm/addrspace.h>
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#include <asm/machvec.h>
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#include <asm/pgtable.h>
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#include <asm-generic/iomap.h>
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#ifdef __KERNEL__
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/*
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* Depending on which platform we are running on, we need different
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* I/O functions.
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*/
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#define __IO_PREFIX generic
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#include <asm/io_generic.h>
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#include <asm/io_trapped.h>
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#define inb(p) sh_mv.mv_inb((p))
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#define inw(p) sh_mv.mv_inw((p))
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#define inl(p) sh_mv.mv_inl((p))
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#define outb(x,p) sh_mv.mv_outb((x),(p))
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#define outw(x,p) sh_mv.mv_outw((x),(p))
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#define outl(x,p) sh_mv.mv_outl((x),(p))
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#define inb_p(p) sh_mv.mv_inb_p((p))
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#define inw_p(p) sh_mv.mv_inw_p((p))
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#define inl_p(p) sh_mv.mv_inl_p((p))
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#define outb_p(x,p) sh_mv.mv_outb_p((x),(p))
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#define outw_p(x,p) sh_mv.mv_outw_p((x),(p))
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#define outl_p(x,p) sh_mv.mv_outl_p((x),(p))
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#define insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
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#define insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
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#define insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
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#define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
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#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
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#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
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#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
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#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
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#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
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#define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
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#define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
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#define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
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#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
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#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
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#define readb(a) ({ u8 r_ = __raw_readb(a); mb(); r_; })
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#define readw(a) ({ u16 r_ = __raw_readw(a); mb(); r_; })
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#define readl(a) ({ u32 r_ = __raw_readl(a); mb(); r_; })
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#define readq(a) ({ u64 r_ = __raw_readq(a); mb(); r_; })
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#define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
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#define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
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#define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
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#define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); })
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/* SuperH on-chip I/O functions */
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#define ctrl_inb __raw_readb
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#define ctrl_inw __raw_readw
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#define ctrl_inl __raw_readl
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#define ctrl_inq __raw_readq
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#define ctrl_outb __raw_writeb
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#define ctrl_outw __raw_writew
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#define ctrl_outl __raw_writel
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#define ctrl_outq __raw_writeq
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static inline void ctrl_delay(void)
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{
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#ifdef P2SEG
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__raw_readw(P2SEG);
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#endif
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}
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#define __BUILD_MEMORY_STRING(bwlq, type) \
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\
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static inline void __raw_writes##bwlq(volatile void __iomem *mem, \
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const void *addr, unsigned int count) \
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{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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__raw_write##bwlq(*__addr, mem); \
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__addr++; \
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} \
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} \
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\
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static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
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void *addr, unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __raw_read##bwlq(mem); \
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__addr++; \
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} \
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}
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__BUILD_MEMORY_STRING(b, u8)
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__BUILD_MEMORY_STRING(w, u16)
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__BUILD_MEMORY_STRING(q, u64)
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void __raw_writesl(void __iomem *addr, const void *data, int longlen);
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void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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#define writesb __raw_writesb
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#define writesw __raw_writesw
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#define writesl __raw_writesl
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#define readsb __raw_readsb
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#define readsw __raw_readsw
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#define readsl __raw_readsl
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#define readb_relaxed(a) readb(a)
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#define readw_relaxed(a) readw(a)
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#define readl_relaxed(a) readl(a)
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#define readq_relaxed(a) readq(a)
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/* Simple MMIO */
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#define ioread8(a) __raw_readb(a)
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#define ioread16(a) __raw_readw(a)
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#define ioread16be(a) be16_to_cpu(__raw_readw((a)))
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#define ioread32(a) __raw_readl(a)
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#define ioread32be(a) be32_to_cpu(__raw_readl((a)))
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#define iowrite8(v,a) __raw_writeb((v),(a))
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#define iowrite16(v,a) __raw_writew((v),(a))
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#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
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#define iowrite32(v,a) __raw_writel((v),(a))
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#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
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#define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c))
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#define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c))
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#define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c))
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#define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c))
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#define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
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#define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
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/* synco on SH-4A, otherwise a nop */
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#define mmiowb() wmb()
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#define IO_SPACE_LIMIT 0xffffffff
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extern unsigned long generic_io_base;
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/*
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* This function provides a method for the generic case where a
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* board-specific ioport_map simply needs to return the port + some
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* arbitrary port base.
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*
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* We use this at board setup time to implicitly set the port base, and
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* as a result, we can use the generic ioport_map.
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*/
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static inline void __set_io_port_base(unsigned long pbase)
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{
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generic_io_base = pbase;
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}
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#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
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/* We really want to try and get these to memcpy etc */
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void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
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void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
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void memset_io(volatile void __iomem *, int, unsigned long);
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/* Quad-word real-mode I/O, don't ask.. */
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unsigned long long peek_real_address_q(unsigned long long addr);
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unsigned long long poke_real_address_q(unsigned long long addr,
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unsigned long long val);
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#if !defined(CONFIG_MMU)
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#define virt_to_phys(address) ((unsigned long)(address))
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#define phys_to_virt(address) ((void *)(address))
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#else
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#define virt_to_phys(address) (__pa(address))
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#define phys_to_virt(address) (__va(address))
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#endif
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/*
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* On 32-bit SH, we traditionally have the whole physical address space
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* mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
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* not need to do anything but place the address in the proper segment.
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* This is true for P1 and P2 addresses, as well as some P3 ones.
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* However, most of the P3 addresses and newer cores using extended
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* addressing need to map through page tables, so the ioremap()
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* implementation becomes a bit more complicated.
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*
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* See arch/sh/mm/ioremap.c for additional notes on this.
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*
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* We cheat a bit and always return uncachable areas until we've fixed
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* the drivers to handle caching properly.
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*
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* On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
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* doesn't exist, so everything must go through page tables.
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*/
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#ifdef CONFIG_MMU
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void __iomem *__ioremap(unsigned long offset, unsigned long size,
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unsigned long flags);
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void __iounmap(void __iomem *addr);
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/* arch/sh/mm/ioremap_64.c */
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unsigned long onchip_remap(unsigned long addr, unsigned long size,
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const char *name);
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extern void onchip_unmap(unsigned long vaddr);
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#else
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#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
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#define __iounmap(addr) do { } while (0)
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#define onchip_remap(addr, size, name) (addr)
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#define onchip_unmap(addr) do { } while (0)
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#endif /* CONFIG_MMU */
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static inline void __iomem *
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__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
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{
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#ifdef CONFIG_SUPERH32
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unsigned long last_addr = offset + size - 1;
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#endif
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void __iomem *ret;
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ret = __ioremap_trapped(offset, size);
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if (ret)
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return ret;
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#ifdef CONFIG_SUPERH32
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/*
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* For P1 and P2 space this is trivial, as everything is already
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* mapped. Uncached access for P1 addresses are done through P2.
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* In the P3 case or for addresses outside of the 29-bit space,
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* mapping must be done by the PMB or by using page tables.
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*/
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if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
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if (unlikely(flags & _PAGE_CACHABLE))
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return (void __iomem *)P1SEGADDR(offset);
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return (void __iomem *)P2SEGADDR(offset);
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}
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#endif
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return __ioremap(offset, size, flags);
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}
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#define ioremap(offset, size) \
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__ioremap_mode((offset), (size), 0)
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#define ioremap_nocache(offset, size) \
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__ioremap_mode((offset), (size), 0)
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#define ioremap_cache(offset, size) \
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__ioremap_mode((offset), (size), _PAGE_CACHABLE)
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#define p3_ioremap(offset, size, flags) \
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__ioremap((offset), (size), (flags))
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#define ioremap_prot(offset, size, flags) \
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__ioremap_mode((offset), (size), (flags))
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#define iounmap(addr) \
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__iounmap((addr))
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#define maybebadio(port) \
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printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
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__func__, __LINE__, (port), (u32)__builtin_return_address(0))
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_IO_H */
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