![Andre Przywara](/assets/img/avatar_default.png)
With all the necessary GICv3 emulation code in place, we can now connect the code to the GICv3 backend in the kernel. The LR register handling is different depending on the emulated GIC model, so provide different implementations for each. Also allow non-v2-compatible GICv3 implementations (which don't provide MMIO regions for the virtual CPU interface in the DT), but restrict those hosts to support GICv3 guests only. If the device tree provides a GICv2 compatible GICV resource entry, but that one is faulty, just disable the GICv2 emulation and let the user use at least the GICv3 emulation for guests. To provide proper support for the legacy KVM_CREATE_IRQCHIP ioctl, note virtual GICv2 compatibility in struct vgic_params and use it on creating a VGICv2. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
280 lines
7.9 KiB
C
280 lines
7.9 KiB
C
/*
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* Copyright (C) 2013 ARM Limited, All Rights Reserved.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cpu.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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/* These are for GICv2 emulation only */
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#define GICH_LR_VIRTUALID (0x3ffUL << 0)
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#define GICH_LR_PHYSID_CPUID_SHIFT (10)
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#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
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#define ICH_LR_VIRTUALID_MASK (BIT_ULL(32) - 1)
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/*
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* LRs are stored in reverse order in memory. make sure we index them
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* correctly.
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*/
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#define LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
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static u32 ich_vtr_el2;
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static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
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{
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struct vgic_lr lr_desc;
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u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)];
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if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
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lr_desc.irq = val & ICH_LR_VIRTUALID_MASK;
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else
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lr_desc.irq = val & GICH_LR_VIRTUALID;
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lr_desc.source = 0;
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if (lr_desc.irq <= 15 &&
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vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
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lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
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lr_desc.state = 0;
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if (val & ICH_LR_PENDING_BIT)
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lr_desc.state |= LR_STATE_PENDING;
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if (val & ICH_LR_ACTIVE_BIT)
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lr_desc.state |= LR_STATE_ACTIVE;
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if (val & ICH_LR_EOI)
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lr_desc.state |= LR_EOI_INT;
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return lr_desc;
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}
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static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
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struct vgic_lr lr_desc)
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{
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u64 lr_val;
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lr_val = lr_desc.irq;
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/*
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* Currently all guest IRQs are Group1, as Group0 would result
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* in a FIQ in the guest, which it wouldn't expect.
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* Eventually we want to make this configurable, so we may revisit
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* this in the future.
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*/
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if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
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lr_val |= ICH_LR_GROUP;
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else
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lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
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if (lr_desc.state & LR_STATE_PENDING)
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lr_val |= ICH_LR_PENDING_BIT;
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if (lr_desc.state & LR_STATE_ACTIVE)
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lr_val |= ICH_LR_ACTIVE_BIT;
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if (lr_desc.state & LR_EOI_INT)
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lr_val |= ICH_LR_EOI;
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vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)] = lr_val;
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}
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static void vgic_v3_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
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struct vgic_lr lr_desc)
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{
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if (!(lr_desc.state & LR_STATE_MASK))
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vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr);
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}
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static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
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}
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static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
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}
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static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
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{
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u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
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u32 ret = 0;
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if (misr & ICH_MISR_EOI)
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ret |= INT_STATUS_EOI;
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if (misr & ICH_MISR_U)
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ret |= INT_STATUS_UNDERFLOW;
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return ret;
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}
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static void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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{
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u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
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vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
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vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
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vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
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vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
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}
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static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr |= ICH_HCR_UIE;
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}
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static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
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}
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static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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{
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u32 vmcr;
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vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
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vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
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vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
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vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
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vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
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}
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static void vgic_v3_enable(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
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/*
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* By forcing VMCR to zero, the GIC will restore the binary
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* points to their reset values. Anything else resets to zero
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* anyway.
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*/
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vgic_v3->vgic_vmcr = 0;
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/*
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* If we are emulating a GICv3, we do it in an non-GICv2-compatible
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* way, so we force SRE to 1 to demonstrate this to the guest.
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* This goes with the spec allowing the value to be RAO/WI.
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*/
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if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
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vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
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else
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vgic_v3->vgic_sre = 0;
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/* Get the show on the road... */
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vgic_v3->vgic_hcr = ICH_HCR_EN;
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}
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static const struct vgic_ops vgic_v3_ops = {
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.get_lr = vgic_v3_get_lr,
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.set_lr = vgic_v3_set_lr,
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.sync_lr_elrsr = vgic_v3_sync_lr_elrsr,
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.get_elrsr = vgic_v3_get_elrsr,
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.get_eisr = vgic_v3_get_eisr,
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.get_interrupt_status = vgic_v3_get_interrupt_status,
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.enable_underflow = vgic_v3_enable_underflow,
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.disable_underflow = vgic_v3_disable_underflow,
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.get_vmcr = vgic_v3_get_vmcr,
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.set_vmcr = vgic_v3_set_vmcr,
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.enable = vgic_v3_enable,
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};
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static struct vgic_params vgic_v3_params;
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/**
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* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
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* @node: pointer to the DT node
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* @ops: address of a pointer to the GICv3 operations
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* @params: address of a pointer to HW-specific parameters
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*
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* Returns 0 if a GICv3 has been found, with the low level operations
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* in *ops and the HW parameters in *params. Returns an error code
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* otherwise.
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*/
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int vgic_v3_probe(struct device_node *vgic_node,
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const struct vgic_ops **ops,
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const struct vgic_params **params)
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{
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int ret = 0;
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u32 gicv_idx;
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struct resource vcpu_res;
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struct vgic_params *vgic = &vgic_v3_params;
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vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
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if (!vgic->maint_irq) {
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kvm_err("error getting vgic maintenance irq from DT\n");
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ret = -ENXIO;
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goto out;
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}
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ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
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/*
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* The ListRegs field is 5 bits, but there is a architectural
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* maximum of 16 list registers. Just ignore bit 4...
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*/
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vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
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vgic->can_emulate_gicv2 = false;
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if (of_property_read_u32(vgic_node, "#redistributor-regions", &gicv_idx))
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gicv_idx = 1;
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gicv_idx += 3; /* Also skip GICD, GICC, GICH */
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if (of_address_to_resource(vgic_node, gicv_idx, &vcpu_res)) {
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kvm_info("GICv3: no GICV resource entry\n");
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vgic->vcpu_base = 0;
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} else if (!PAGE_ALIGNED(vcpu_res.start)) {
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pr_warn("GICV physical address 0x%llx not page aligned\n",
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(unsigned long long)vcpu_res.start);
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vgic->vcpu_base = 0;
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} else if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
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pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
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(unsigned long long)resource_size(&vcpu_res),
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PAGE_SIZE);
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vgic->vcpu_base = 0;
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} else {
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vgic->vcpu_base = vcpu_res.start;
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vgic->can_emulate_gicv2 = true;
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kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
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KVM_DEV_TYPE_ARM_VGIC_V2);
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}
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if (vgic->vcpu_base == 0)
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kvm_info("disabling GICv2 emulation\n");
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kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);
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vgic->vctrl_base = NULL;
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vgic->type = VGIC_V3;
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vgic->max_gic_vcpus = KVM_MAX_VCPUS;
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kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
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vcpu_res.start, vgic->maint_irq);
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*ops = &vgic_v3_ops;
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*params = vgic;
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out:
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of_node_put(vgic_node);
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return ret;
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}
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