![Stefan Wahren](/assets/img/avatar_default.png)
According to the BCM2835 datasheet the maximum block size for the eMMC module is restricted to the internal data FIFO which is 1024 byte. But this is still an improvement to the default of 512 byte. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
309 lines
8.7 KiB
C
309 lines
8.7 KiB
C
/*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* iProc SDHCI platform driver
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*/
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/mmc/host.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "sdhci-pltfm.h"
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struct sdhci_iproc_data {
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const struct sdhci_pltfm_data *pdata;
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u32 caps;
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u32 caps1;
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u32 mmc_caps;
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};
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struct sdhci_iproc_host {
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const struct sdhci_iproc_data *data;
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u32 shadow_cmd;
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u32 shadow_blk;
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};
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#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
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static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
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{
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u32 val = readl(host->ioaddr + reg);
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pr_debug("%s: readl [0x%02x] 0x%08x\n",
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mmc_hostname(host->mmc), reg, val);
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return val;
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}
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static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
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{
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u32 val = sdhci_iproc_readl(host, (reg & ~3));
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u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
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return word;
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}
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static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
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{
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u32 val = sdhci_iproc_readl(host, (reg & ~3));
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u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
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return byte;
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}
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static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
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{
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pr_debug("%s: writel [0x%02x] 0x%08x\n",
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mmc_hostname(host->mmc), reg, val);
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writel(val, host->ioaddr + reg);
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if (host->clock <= 400000) {
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/* Round up to micro-second four SD clock delay */
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if (host->clock)
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udelay((4 * 1000000 + host->clock - 1) / host->clock);
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else
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udelay(10);
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}
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}
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/*
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* The Arasan has a bugette whereby it may lose the content of successive
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* writes to the same register that are within two SD-card clock cycles of
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* each other (a clock domain crossing problem). The data
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* register does not have this problem, which is just as well - otherwise we'd
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* have to nobble the DMA engine too.
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*
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* This wouldn't be a problem with the code except that we can only write the
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* controller with 32-bit writes. So two different 16-bit registers are
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* written back to back creates the problem.
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*
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* In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
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* are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
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* The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
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* the work around can be further optimized. We can keep shadow values of
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* BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
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* Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
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* by the TRANSFER+COMMAND in another 32-bit write.
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*/
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static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
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u32 word_shift = REG_OFFSET_IN_BITS(reg);
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u32 mask = 0xffff << word_shift;
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u32 oldval, newval;
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if (reg == SDHCI_COMMAND) {
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/* Write the block now as we are issuing a command */
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if (iproc_host->shadow_blk != 0) {
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sdhci_iproc_writel(host, iproc_host->shadow_blk,
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SDHCI_BLOCK_SIZE);
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iproc_host->shadow_blk = 0;
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}
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oldval = iproc_host->shadow_cmd;
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} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
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/* Block size and count are stored in shadow reg */
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oldval = iproc_host->shadow_blk;
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} else {
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/* Read reg, all other registers are not shadowed */
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oldval = sdhci_iproc_readl(host, (reg & ~3));
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}
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newval = (oldval & ~mask) | (val << word_shift);
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if (reg == SDHCI_TRANSFER_MODE) {
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/* Save the transfer mode until the command is issued */
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iproc_host->shadow_cmd = newval;
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} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
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/* Save the block info until the command is issued */
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iproc_host->shadow_blk = newval;
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} else {
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/* Command or other regular 32-bit write */
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sdhci_iproc_writel(host, newval, reg & ~3);
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}
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}
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static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
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u32 byte_shift = REG_OFFSET_IN_BITS(reg);
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u32 mask = 0xff << byte_shift;
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u32 newval = (oldval & ~mask) | (val << byte_shift);
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sdhci_iproc_writel(host, newval, reg & ~3);
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}
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static const struct sdhci_ops sdhci_iproc_ops = {
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.set_clock = sdhci_set_clock,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_ops sdhci_iproc_32only_ops = {
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.read_l = sdhci_iproc_readl,
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.read_w = sdhci_iproc_readw,
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.read_b = sdhci_iproc_readb,
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.write_l = sdhci_iproc_writel,
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.write_w = sdhci_iproc_writew,
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.write_b = sdhci_iproc_writeb,
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.set_clock = sdhci_set_clock,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
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.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
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.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
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.ops = &sdhci_iproc_32only_ops,
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};
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static const struct sdhci_iproc_data iproc_cygnus_data = {
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.pdata = &sdhci_iproc_cygnus_pltfm_data,
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.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
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& SDHCI_MAX_BLOCK_MASK) |
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SDHCI_CAN_VDD_330 |
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SDHCI_CAN_VDD_180 |
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SDHCI_CAN_DO_SUSPEND |
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SDHCI_CAN_DO_HISPD |
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SDHCI_CAN_DO_ADMA2 |
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SDHCI_CAN_DO_SDMA,
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.caps1 = SDHCI_DRIVER_TYPE_C |
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SDHCI_DRIVER_TYPE_D |
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SDHCI_SUPPORT_DDR50,
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.mmc_caps = MMC_CAP_1_8V_DDR,
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};
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static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
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.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
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.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
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.ops = &sdhci_iproc_ops,
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};
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static const struct sdhci_iproc_data iproc_data = {
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.pdata = &sdhci_iproc_pltfm_data,
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.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
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& SDHCI_MAX_BLOCK_MASK) |
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SDHCI_CAN_VDD_330 |
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SDHCI_CAN_VDD_180 |
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SDHCI_CAN_DO_SUSPEND |
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SDHCI_CAN_DO_HISPD |
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SDHCI_CAN_DO_ADMA2 |
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SDHCI_CAN_DO_SDMA,
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.caps1 = SDHCI_DRIVER_TYPE_C |
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SDHCI_DRIVER_TYPE_D |
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SDHCI_SUPPORT_DDR50,
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.mmc_caps = MMC_CAP_1_8V_DDR,
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};
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static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
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.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_MISSING_CAPS |
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SDHCI_QUIRK_NO_HISPD_BIT,
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.ops = &sdhci_iproc_32only_ops,
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};
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static const struct sdhci_iproc_data bcm2835_data = {
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.pdata = &sdhci_bcm2835_pltfm_data,
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.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
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& SDHCI_MAX_BLOCK_MASK) |
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SDHCI_CAN_VDD_330 |
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SDHCI_CAN_DO_HISPD,
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.caps1 = SDHCI_DRIVER_TYPE_A |
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SDHCI_DRIVER_TYPE_C,
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.mmc_caps = 0x00000000,
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};
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static const struct of_device_id sdhci_iproc_of_match[] = {
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{ .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
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{ .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
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{ .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
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static int sdhci_iproc_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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const struct sdhci_iproc_data *iproc_data;
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struct sdhci_host *host;
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struct sdhci_iproc_host *iproc_host;
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struct sdhci_pltfm_host *pltfm_host;
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int ret;
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match = of_match_device(sdhci_iproc_of_match, &pdev->dev);
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if (!match)
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return -EINVAL;
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iproc_data = match->data;
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host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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iproc_host = sdhci_pltfm_priv(pltfm_host);
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iproc_host->data = iproc_data;
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mmc_of_parse(host->mmc);
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sdhci_get_of_property(pdev);
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host->mmc->caps |= iproc_host->data->mmc_caps;
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pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pltfm_host->clk)) {
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ret = PTR_ERR(pltfm_host->clk);
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goto err;
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}
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ret = clk_prepare_enable(pltfm_host->clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable host clk\n");
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goto err;
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}
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if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
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host->caps = iproc_host->data->caps;
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host->caps1 = iproc_host->data->caps1;
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}
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ret = sdhci_add_host(host);
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if (ret)
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goto err_clk;
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return 0;
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err_clk:
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clk_disable_unprepare(pltfm_host->clk);
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err:
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sdhci_pltfm_free(pdev);
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return ret;
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}
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static struct platform_driver sdhci_iproc_driver = {
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.driver = {
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.name = "sdhci-iproc",
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.of_match_table = sdhci_iproc_of_match,
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.pm = &sdhci_pltfm_pmops,
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},
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.probe = sdhci_iproc_probe,
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.remove = sdhci_pltfm_unregister,
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};
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module_platform_driver(sdhci_iproc_driver);
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MODULE_AUTHOR("Broadcom");
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MODULE_DESCRIPTION("IPROC SDHCI driver");
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MODULE_LICENSE("GPL v2");
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