![Tobin C. Harding](/assets/img/avatar_default.png)
Pre-processor header guards use double underscore, typically kernel code uses single underscore when defining header guards. 'endif' statement should include what is ending as a comment string. Remove double underscore, add comment string to 'endif' Signed-off-by: Tobin C. Harding <me@tobin.cc> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
176 lines
5.6 KiB
C
176 lines
5.6 KiB
C
/*
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* Copyright 2003 Digi International (www.digi.com)
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* Scott H Kilau <Scott_Kilau at digi dot com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
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* implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*/
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#ifndef _DGNC_NEO_H
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#define _DGNC_NEO_H
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#include "dgnc_driver.h"
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/**
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* struct neo_uart_struct - Per channel/port NEO UART structure
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*
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* key - W = read write
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* - R = read only
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* - U = unused
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*
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* @txrx: (RW) Holding Register.
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* @ier: (RW) Interrupt Enable Register.
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* @isr_fcr: (RW) Interrupt Status Reg/Fifo Control Register.
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* @lcr: (RW) Line Control Register.
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* @mcr: (RW) Modem Control Register.
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* @lsr: (RW) Line Status Register.
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* @msr: (RW) Modem Status Register.
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* @spr: (RW) Scratch Pad Register.
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* @fctr: (RW) Feature Control Register.
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* @efr: (RW) Enhanced Function Register.
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* @tfifo: (RW) Transmit FIFO Register.
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* @rfifo: (RW) Receive FIFO Register.
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* @xoffchar1: (RW) XOff Character 1 Register.
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* @xoffchar2: (RW) XOff Character 2 Register.
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* @xonchar1: (RW) Xon Character 1 Register.
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* @xonchar2: (RW) XOn Character 2 Register.
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* @reserved1: (U) Reserved by Exar.
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* @txrxburst: (RW) 64 bytes of RX/TX FIFO Data.
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* @reserved2: (U) Reserved by Exar.
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* @rxburst_with_errors: (R) bytes of RX FIFO Data + LSR.
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*/
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struct neo_uart_struct {
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u8 txrx;
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u8 ier;
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u8 isr_fcr;
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u8 lcr;
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u8 mcr;
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u8 lsr;
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u8 msr;
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u8 spr;
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u8 fctr;
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u8 efr;
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u8 tfifo;
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u8 rfifo;
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u8 xoffchar1;
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u8 xoffchar2;
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u8 xonchar1;
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u8 xonchar2;
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u8 reserved1[0x2ff - 0x200];
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u8 txrxburst[64];
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u8 reserved2[0x37f - 0x340];
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u8 rxburst_with_errors[64];
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};
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/* Where to read the extended interrupt register (32bits instead of 8bits) */
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#define UART_17158_POLL_ADDR_OFFSET 0x80
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/* These are the current dvid's of the Neo boards */
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#define UART_XR17C158_DVID 0x20
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#define UART_XR17D158_DVID 0x20
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#define UART_XR17E158_DVID 0x40
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#define NEO_EECK 0x10 /* Clock */
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#define NEO_EECS 0x20 /* Chip Select */
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#define NEO_EEDI 0x40 /* Data In is an Output Pin */
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#define NEO_EEDO 0x80 /* Data Out is an Input Pin */
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#define NEO_EEREG 0x8E /* offset to EEPROM control reg */
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#define NEO_VPD_IMAGESIZE 0x40 /* size of image to read from EEPROM in words */
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#define NEO_VPD_IMAGEBYTES (NEO_VPD_IMAGESIZE * 2)
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/*
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* These are the redefinitions for the FCTR on the XR17C158, since
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* Exar made them different than their earlier design. (XR16C854)
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*/
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/* These are only applicable when table D is selected */
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#define UART_17158_FCTR_RTS_NODELAY 0x00
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#define UART_17158_FCTR_RTS_4DELAY 0x01
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#define UART_17158_FCTR_RTS_6DELAY 0x02
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#define UART_17158_FCTR_RTS_8DELAY 0x03
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#define UART_17158_FCTR_RTS_12DELAY 0x12
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#define UART_17158_FCTR_RTS_16DELAY 0x05
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#define UART_17158_FCTR_RTS_20DELAY 0x13
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#define UART_17158_FCTR_RTS_24DELAY 0x06
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#define UART_17158_FCTR_RTS_28DELAY 0x14
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#define UART_17158_FCTR_RTS_32DELAY 0x07
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#define UART_17158_FCTR_RTS_36DELAY 0x16
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#define UART_17158_FCTR_RTS_40DELAY 0x08
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#define UART_17158_FCTR_RTS_44DELAY 0x09
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#define UART_17158_FCTR_RTS_48DELAY 0x10
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#define UART_17158_FCTR_RTS_52DELAY 0x11
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#define UART_17158_FCTR_RTS_IRDA 0x10
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#define UART_17158_FCTR_RS485 0x20
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#define UART_17158_FCTR_TRGA 0x00
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#define UART_17158_FCTR_TRGB 0x40
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#define UART_17158_FCTR_TRGC 0x80
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#define UART_17158_FCTR_TRGD 0xC0
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/* 17158 trigger table selects.. */
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#define UART_17158_FCTR_BIT6 0x40
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#define UART_17158_FCTR_BIT7 0x80
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/* 17158 TX/RX memmapped buffer offsets */
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#define UART_17158_RX_FIFOSIZE 64
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#define UART_17158_TX_FIFOSIZE 64
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/* 17158 Extended IIR's */
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#define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
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#define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
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#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR
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* state change
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*/
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#define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
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/*
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* These are the extended interrupts that get sent
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* back to us from the UART's 32bit interrupt register
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*/
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#define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
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#define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
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#define UART_17158_TXRDY 0x3 /* TX Ready */
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#define UART_17158_MSR 0x4 /* Modem State Change */
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#define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding
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* Reg Empty
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*/
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#define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO
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* Data error
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*/
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/*
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* These are the EXTENDED definitions for the 17C158's Interrupt
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* Enable Register.
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*/
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#define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
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#define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
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#define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
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#define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
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#define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow Control Enable */
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#define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an
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* incoming XOFF char
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*/
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#define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an
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* incoming XON char
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*/
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#define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
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#define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
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#define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
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#define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
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extern struct board_ops dgnc_neo_ops;
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#endif /* _DGNC_NEO_H */
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