f8e9f34f80
Pass struct musb to tusb_dma_omap() and is_cppi_enabled(), and add macros for the other DMA controllers. Populate the platform specific quirks with the DMA type and use it during runtime. Note that platform glue layers with no custom DMA code are tagged with MUSB_DMA_INVENTRA which may have a chance of working. Looks like the defconfigs for these use PIO_ONLY, so this should not break existing configs. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
219 lines
9 KiB
C
219 lines
9 KiB
C
/*
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* Definitions for TUSB6010 USB 2.0 OTG Dual Role controller
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __TUSB6010_H__
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#define __TUSB6010_H__
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/* VLYNQ control register. 32-bit at offset 0x000 */
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#define TUSB_VLYNQ_CTRL 0x004
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/* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
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#define TUSB_BASE_OFFSET 0x400
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/* FIFO registers 32-bit at offset 0x600 */
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#define TUSB_FIFO_BASE 0x600
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/* Device System & Control registers. 32-bit at offset 0x800 */
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#define TUSB_SYS_REG_BASE 0x800
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#define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
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#define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16)
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#define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15)
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#define TUSB_DEV_CONF_SOFT_ID (1 << 1)
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#define TUSB_DEV_CONF_ID_SEL (1 << 0)
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#define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
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#define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
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#define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24)
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#define TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP (1 << 23)
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#define TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN (1 << 19)
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#define TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN (1 << 18)
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#define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17)
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#define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16)
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#define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15)
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#define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14)
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#define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13)
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#define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12)
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#define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11)
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#define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10)
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#define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9)
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#define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7)
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#define TUSB_PHY_OTG_CTRL_PD (1 << 6)
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#define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5)
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#define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4)
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#define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3)
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#define TUSB_PHY_OTG_CTRL_RESET (1 << 2)
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#define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1)
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#define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0)
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/*OTG status register */
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#define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
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#define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8)
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#define TUSB_DEV_OTG_STAT_SESS_END (1 << 7)
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#define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6)
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#define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5)
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#define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4)
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#define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3)
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#define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2)
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#define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0)
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#define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1)
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#define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0)
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#define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
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# define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31)
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# define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
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#define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
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/* PRCM configuration register */
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#define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
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#define TUSB_PRCM_CONF_SFW_CPEN (1 << 24)
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#define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16)
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/* PRCM management register */
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#define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
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#define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25)
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#define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24)
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#define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20)
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#define TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN (1 << 19)
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#define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18)
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#define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17)
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#define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
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#define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
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#define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8)
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#define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4)
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#define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3)
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#define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2)
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#define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1)
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#define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0)
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/* Wake-up source clear and mask registers */
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#define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
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#define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
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#define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
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#define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13)
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#define TUSB_PRCM_WGPIO_7 (1 << 12)
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#define TUSB_PRCM_WGPIO_6 (1 << 11)
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#define TUSB_PRCM_WGPIO_5 (1 << 10)
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#define TUSB_PRCM_WGPIO_4 (1 << 9)
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#define TUSB_PRCM_WGPIO_3 (1 << 8)
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#define TUSB_PRCM_WGPIO_2 (1 << 7)
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#define TUSB_PRCM_WGPIO_1 (1 << 6)
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#define TUSB_PRCM_WGPIO_0 (1 << 5)
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#define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */
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#define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */
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#define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */
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#define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */
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#define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */
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#define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
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#define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
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#define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
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#define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
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#define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
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#define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
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#define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
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#define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
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#define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
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#define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
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#define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
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#define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
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#define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
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#define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
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#define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
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#define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
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/* NOR flash interrupt source registers */
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#define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
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#define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
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#define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
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#define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
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#define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24)
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#define TUSB_INT_SRC_USB_IP_CORE (1 << 17)
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#define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16)
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#define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15)
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#define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14)
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#define TUSB_INT_SRC_DEV_WAKEUP (1 << 13)
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#define TUSB_INT_SRC_DEV_READY (1 << 12)
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#define TUSB_INT_SRC_USB_IP_TX (1 << 9)
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#define TUSB_INT_SRC_USB_IP_RX (1 << 8)
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#define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7)
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#define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6)
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#define TUSB_INT_SRC_USB_IP_DISCON (1 << 5)
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#define TUSB_INT_SRC_USB_IP_CONN (1 << 4)
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#define TUSB_INT_SRC_USB_IP_SOF (1 << 3)
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#define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2)
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#define TUSB_INT_SRC_USB_IP_RESUME (1 << 1)
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#define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0)
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/* NOR flash interrupt registers reserved bits. Must be written as 0 */
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#define TUSB_INT_MASK_RESERVED_17 (0x3fff << 17)
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#define TUSB_INT_MASK_RESERVED_13 (1 << 13)
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#define TUSB_INT_MASK_RESERVED_8 (0xf << 8)
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#define TUSB_INT_SRC_RESERVED_26 (0x1f << 26)
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#define TUSB_INT_SRC_RESERVED_18 (0x3f << 18)
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#define TUSB_INT_SRC_RESERVED_10 (0x03 << 10)
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/* Reserved bits for NOR flash interrupt mask and clear register */
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#define TUSB_INT_MASK_RESERVED_BITS (TUSB_INT_MASK_RESERVED_17 | \
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TUSB_INT_MASK_RESERVED_13 | \
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TUSB_INT_MASK_RESERVED_8)
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/* Reserved bits for NOR flash interrupt status register */
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#define TUSB_INT_SRC_RESERVED_BITS (TUSB_INT_SRC_RESERVED_26 | \
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TUSB_INT_SRC_RESERVED_18 | \
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TUSB_INT_SRC_RESERVED_10)
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#define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
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#define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
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#define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
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#define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
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#define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
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#define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
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/* Offsets from each ep base register */
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#define TUSB_EP_TX_OFFSET 0x10c /* EP_IN in docs */
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#define TUSB_EP_RX_OFFSET 0x14c /* EP_OUT in docs */
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#define TUSB_EP_MAX_PACKET_SIZE_OFFSET 0x188
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#define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
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#define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
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#define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
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/* Device System & Control register bitfields */
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#define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18)
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#define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
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#define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16)
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#define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
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#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
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#define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20)
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#define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16)
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#define TUSB_EP0_CONFIG_SW_EN (1 << 8)
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#define TUSB_EP0_CONFIG_DIR_TX (1 << 7)
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#define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
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#define TUSB_EP_CONFIG_SW_EN (1 << 31)
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#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
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#define TUSB_PROD_TEST_RESET_VAL 0xa596
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#define TUSB_EP_FIFO(ep) (TUSB_FIFO_BASE + (ep) * 0x20)
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#define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
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#define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)
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#define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf)
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#define TUSB_DIDR1_HI_REV_20 0
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#define TUSB_DIDR1_HI_REV_30 1
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#define TUSB_DIDR1_HI_REV_31 2
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#define TUSB_REV_10 0x10
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#define TUSB_REV_20 0x20
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#define TUSB_REV_30 0x30
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#define TUSB_REV_31 0x31
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#endif /* __TUSB6010_H__ */
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