a439fe51a1
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
37 lines
1 KiB
C
37 lines
1 KiB
C
/*
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* apb.h: Advanced PCI Bridge Configuration Registers and Bits
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*
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* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
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*/
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#ifndef _SPARC64_APB_H
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#define _SPARC64_APB_H
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#define APB_TICK_REGISTER 0xb0
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#define APB_INT_ACK 0xb8
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#define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0
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#define APB_DMA_ASFR 0xc8
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#define APB_DMA_AFAR 0xd0
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#define APB_PIO_TARGET_RETRY_LIMIT 0xd8
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#define APB_PIO_TARGET_LATENCY_TIMER 0xd9
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#define APB_DMA_TARGET_RETRY_LIMIT 0xda
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#define APB_DMA_TARGET_LATENCY_TIMER 0xdb
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#define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc
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#define APB_SECONDARY_CONTROL 0xdd
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#define APB_IO_ADDRESS_MAP 0xde
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#define APB_MEM_ADDRESS_MAP 0xdf
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#define APB_PCI_CONTROL_LOW 0xe0
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# define APB_PCI_CTL_LOW_ARB_PARK (1 << 21)
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# define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8)
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#define APB_PCI_CONTROL_HIGH 0xe4
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# define APB_PCI_CTL_HIGH_SERR (1 << 2)
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# define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0)
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#define APB_PIO_ASFR 0xe8
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#define APB_PIO_AFAR 0xf0
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#define APB_DIAG_REGISTER 0xf8
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#endif /* !(_SPARC64_APB_H) */
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