e360adbe29
Provide a mechanism that allows running code in IRQ context. It is most useful for NMI code that needs to interact with the rest of the system -- like wakeup a task to drain buffers. Perf currently has such a mechanism, so extract that and provide it as a generic feature, independent of perf so that others may also benefit. The IRQ context callback is generated through self-IPIs where possible, or on architectures like powerpc the decrementer (the built-in timer facility) is set to generate an interrupt immediately. Architectures that don't have anything like this get to do with a callback from the timer tick. These architectures can call irq_work_run() at the tail of any IRQ handlers that might enqueue such work (like the perf IRQ handler) to avoid undue latencies in processing the work. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Kyle McMartin <kyle@mcmartin.ca> Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [ various fixes ] Signed-off-by: Huang Ying <ying.huang@intel.com> LKML-Reference: <1287036094.7768.291.camel@yhuang-dev> Signed-off-by: Ingo Molnar <mingo@elte.hu>
34 lines
858 B
C
34 lines
858 B
C
#ifndef __ASM_SPARC_PERF_EVENT_H
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#define __ASM_SPARC_PERF_EVENT_H
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#ifdef CONFIG_PERF_EVENTS
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#include <asm/ptrace.h>
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extern void init_hw_perf_events(void);
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#define perf_arch_fetch_caller_regs(regs, ip) \
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do { \
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unsigned long _pstate, _asi, _pil, _i7, _fp; \
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__asm__ __volatile__("rdpr %%pstate, %0\n\t" \
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"rd %%asi, %1\n\t" \
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"rdpr %%pil, %2\n\t" \
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"mov %%i7, %3\n\t" \
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"mov %%i6, %4\n\t" \
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: "=r" (_pstate), \
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"=r" (_asi), \
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"=r" (_pil), \
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"=r" (_i7), \
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"=r" (_fp)); \
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(regs)->tstate = (_pstate << 8) | \
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(_asi << 24) | (_pil << 20); \
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(regs)->tpc = (ip); \
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(regs)->tnpc = (regs)->tpc + 4; \
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(regs)->u_regs[UREG_I6] = _fp; \
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(regs)->u_regs[UREG_I7] = _i7; \
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} while (0)
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#else
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static inline void init_hw_perf_events(void) { }
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#endif
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#endif
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