476 lines
12 KiB
C
476 lines
12 KiB
C
/*
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <linux/delay.h>
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#include "hfi.h"
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#include "common.h"
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#include "eprom.h"
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/*
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* The EPROM is logically divided into two partitions:
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* partition 0: the first 128K, visible from PCI ROM BAR
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* partition 1: the rest
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*/
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#define P0_SIZE (128 * 1024)
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#define P1_START P0_SIZE
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/* largest erase size supported by the controller */
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#define SIZE_32KB (32 * 1024)
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#define MASK_32KB (SIZE_32KB - 1)
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/* controller page size, in bytes */
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#define EP_PAGE_SIZE 256
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#define EEP_PAGE_MASK (EP_PAGE_SIZE - 1)
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/* controller commands */
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#define CMD_SHIFT 24
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#define CMD_NOP (0)
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#define CMD_PAGE_PROGRAM(addr) ((0x02 << CMD_SHIFT) | addr)
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#define CMD_READ_DATA(addr) ((0x03 << CMD_SHIFT) | addr)
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#define CMD_READ_SR1 ((0x05 << CMD_SHIFT))
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#define CMD_WRITE_ENABLE ((0x06 << CMD_SHIFT))
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#define CMD_SECTOR_ERASE_32KB(addr) ((0x52 << CMD_SHIFT) | addr)
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#define CMD_CHIP_ERASE ((0x60 << CMD_SHIFT))
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#define CMD_READ_MANUF_DEV_ID ((0x90 << CMD_SHIFT))
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#define CMD_RELEASE_POWERDOWN_NOID ((0xab << CMD_SHIFT))
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/* controller interface speeds */
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#define EP_SPEED_FULL 0x2 /* full speed */
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/* controller status register 1 bits */
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#define SR1_BUSY 0x1ull /* the BUSY bit in SR1 */
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/* sleep length while waiting for controller */
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#define WAIT_SLEEP_US 100 /* must be larger than 5 (see usage) */
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#define COUNT_DELAY_SEC(n) ((n) * (1000000/WAIT_SLEEP_US))
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/* GPIO pins */
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#define EPROM_WP_N (1ull << 14) /* EPROM write line */
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/*
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* Use the EP mutex to guard against other callers from within the driver.
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* Also covers usage of eprom_available.
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*/
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static DEFINE_MUTEX(eprom_mutex);
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static int eprom_available; /* default: not available */
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/*
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* Turn on external enable line that allows writing on the flash.
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*/
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static void write_enable(struct hfi1_devdata *dd)
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{
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/* raise signal */
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write_csr(dd, ASIC_GPIO_OUT,
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read_csr(dd, ASIC_GPIO_OUT) | EPROM_WP_N);
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/* raise enable */
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write_csr(dd, ASIC_GPIO_OE,
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read_csr(dd, ASIC_GPIO_OE) | EPROM_WP_N);
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}
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/*
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* Turn off external enable line that allows writing on the flash.
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*/
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static void write_disable(struct hfi1_devdata *dd)
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{
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/* lower signal */
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write_csr(dd, ASIC_GPIO_OUT,
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read_csr(dd, ASIC_GPIO_OUT) & ~EPROM_WP_N);
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/* lower enable */
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write_csr(dd, ASIC_GPIO_OE,
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read_csr(dd, ASIC_GPIO_OE) & ~EPROM_WP_N);
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}
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/*
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* Wait for the device to become not busy. Must be called after all
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* write or erase operations.
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*/
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static int wait_for_not_busy(struct hfi1_devdata *dd)
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{
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unsigned long count = 0;
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u64 reg;
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int ret = 0;
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/* starts page mode */
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_SR1);
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while (1) {
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udelay(WAIT_SLEEP_US);
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usleep_range(WAIT_SLEEP_US - 5, WAIT_SLEEP_US + 5);
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count++;
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reg = read_csr(dd, ASIC_EEP_DATA);
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if ((reg & SR1_BUSY) == 0)
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break;
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/* 200s is the largest time for a 128Mb device */
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if (count > COUNT_DELAY_SEC(200)) {
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dd_dev_err(dd, "waited too long for SPI FLASH busy to clear - failing\n");
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ret = -ETIMEDOUT;
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break; /* break, not goto - must stop page mode */
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}
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}
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/* stop page mode with a NOP */
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP);
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return ret;
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}
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/*
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* Read the device ID from the SPI controller.
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*/
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static u32 read_device_id(struct hfi1_devdata *dd)
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{
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/* read the Manufacture Device ID */
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_MANUF_DEV_ID);
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return (u32)read_csr(dd, ASIC_EEP_DATA);
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}
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/*
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* Erase the whole flash.
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*/
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static int erase_chip(struct hfi1_devdata *dd)
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{
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int ret;
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write_enable(dd);
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_CHIP_ERASE);
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ret = wait_for_not_busy(dd);
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write_disable(dd);
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return ret;
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}
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/*
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* Erase a range using the 32KB erase command.
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*/
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static int erase_32kb_range(struct hfi1_devdata *dd, u32 start, u32 end)
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{
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int ret = 0;
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if (end < start)
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return -EINVAL;
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if ((start & MASK_32KB) || (end & MASK_32KB)) {
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dd_dev_err(dd,
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"%s: non-aligned range (0x%x,0x%x) for a 32KB erase\n",
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__func__, start, end);
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return -EINVAL;
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}
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write_enable(dd);
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for (; start < end; start += SIZE_32KB) {
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
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write_csr(dd, ASIC_EEP_ADDR_CMD,
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CMD_SECTOR_ERASE_32KB(start));
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ret = wait_for_not_busy(dd);
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if (ret)
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goto done;
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}
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done:
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write_disable(dd);
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return ret;
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}
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/*
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* Read a 256 byte (64 dword) EPROM page.
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* All callers have verified the offset is at a page boundary.
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*/
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static void read_page(struct hfi1_devdata *dd, u32 offset, u32 *result)
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{
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int i;
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset));
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for (i = 0; i < EP_PAGE_SIZE/sizeof(u32); i++)
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result[i] = (u32)read_csr(dd, ASIC_EEP_DATA);
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */
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}
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/*
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* Read length bytes starting at offset. Copy to user address addr.
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*/
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static int read_length(struct hfi1_devdata *dd, u32 start, u32 len, u64 addr)
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{
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u32 offset;
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u32 buffer[EP_PAGE_SIZE/sizeof(u32)];
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int ret = 0;
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/* reject anything not on an EPROM page boundary */
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if ((start & EEP_PAGE_MASK) || (len & EEP_PAGE_MASK))
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return -EINVAL;
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for (offset = 0; offset < len; offset += EP_PAGE_SIZE) {
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read_page(dd, start + offset, buffer);
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if (copy_to_user((void __user *)(addr + offset),
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buffer, EP_PAGE_SIZE)) {
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ret = -EFAULT;
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goto done;
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}
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}
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done:
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return ret;
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}
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/*
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* Write a 256 byte (64 dword) EPROM page.
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* All callers have verified the offset is at a page boundary.
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*/
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static int write_page(struct hfi1_devdata *dd, u32 offset, u32 *data)
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{
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int i;
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
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write_csr(dd, ASIC_EEP_DATA, data[0]);
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_PAGE_PROGRAM(offset));
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for (i = 1; i < EP_PAGE_SIZE/sizeof(u32); i++)
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write_csr(dd, ASIC_EEP_DATA, data[i]);
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/* will close the open page */
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return wait_for_not_busy(dd);
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}
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/*
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* Write length bytes starting at offset. Read from user address addr.
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*/
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static int write_length(struct hfi1_devdata *dd, u32 start, u32 len, u64 addr)
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{
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u32 offset;
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u32 buffer[EP_PAGE_SIZE/sizeof(u32)];
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int ret = 0;
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/* reject anything not on an EPROM page boundary */
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if ((start & EEP_PAGE_MASK) || (len & EEP_PAGE_MASK))
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return -EINVAL;
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write_enable(dd);
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for (offset = 0; offset < len; offset += EP_PAGE_SIZE) {
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if (copy_from_user(buffer, (void __user *)(addr + offset),
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EP_PAGE_SIZE)) {
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ret = -EFAULT;
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goto done;
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}
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ret = write_page(dd, start + offset, buffer);
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if (ret)
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goto done;
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}
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done:
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write_disable(dd);
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return ret;
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}
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/*
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* Perform the given operation on the EPROM. Called from user space. The
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* user credentials have already been checked.
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*
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* Return 0 on success, -ERRNO on error
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*/
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int handle_eprom_command(const struct hfi1_cmd *cmd)
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{
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struct hfi1_devdata *dd;
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u32 dev_id;
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int ret = 0;
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/*
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* The EPROM is per-device, so use unit 0 as that will always
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* exist.
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*/
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dd = hfi1_lookup(0);
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if (!dd) {
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pr_err("%s: cannot find unit 0!\n", __func__);
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return -EINVAL;
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}
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/* lock against other callers touching the ASIC block */
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mutex_lock(&eprom_mutex);
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/* some platforms do not have an EPROM */
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if (!eprom_available) {
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ret = -ENOSYS;
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goto done_asic;
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}
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/* lock against the other HFI on another OS */
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ret = acquire_hw_mutex(dd);
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if (ret) {
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dd_dev_err(dd,
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"%s: unable to acquire hw mutex, no EPROM support\n",
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__func__);
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goto done_asic;
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}
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dd_dev_info(dd, "%s: cmd: type %d, len 0x%x, addr 0x%016llx\n",
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__func__, cmd->type, cmd->len, cmd->addr);
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switch (cmd->type) {
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case HFI1_CMD_EP_INFO:
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if (cmd->len != sizeof(u32)) {
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ret = -ERANGE;
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break;
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}
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dev_id = read_device_id(dd);
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/* addr points to a u32 user buffer */
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if (copy_to_user((void __user *)cmd->addr, &dev_id,
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sizeof(u32)))
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ret = -EFAULT;
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break;
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case HFI1_CMD_EP_ERASE_CHIP:
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ret = erase_chip(dd);
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break;
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case HFI1_CMD_EP_ERASE_P0:
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if (cmd->len != P0_SIZE) {
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ret = -ERANGE;
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break;
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}
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ret = erase_32kb_range(dd, 0, cmd->len);
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break;
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case HFI1_CMD_EP_ERASE_P1:
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/* check for overflow */
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if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
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ret = -ERANGE;
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break;
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}
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ret = erase_32kb_range(dd, P1_START, P1_START + cmd->len);
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break;
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case HFI1_CMD_EP_READ_P0:
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if (cmd->len != P0_SIZE) {
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ret = -ERANGE;
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break;
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}
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ret = read_length(dd, 0, cmd->len, cmd->addr);
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break;
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case HFI1_CMD_EP_READ_P1:
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/* check for overflow */
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if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
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ret = -ERANGE;
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break;
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}
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ret = read_length(dd, P1_START, cmd->len, cmd->addr);
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break;
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case HFI1_CMD_EP_WRITE_P0:
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if (cmd->len > P0_SIZE) {
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ret = -ERANGE;
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break;
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}
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ret = write_length(dd, 0, cmd->len, cmd->addr);
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break;
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case HFI1_CMD_EP_WRITE_P1:
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/* check for overflow */
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if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
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ret = -ERANGE;
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break;
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}
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ret = write_length(dd, P1_START, cmd->len, cmd->addr);
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break;
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default:
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dd_dev_err(dd, "%s: unexpected command %d\n",
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__func__, cmd->type);
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ret = -EINVAL;
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break;
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}
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release_hw_mutex(dd);
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done_asic:
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mutex_unlock(&eprom_mutex);
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return ret;
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}
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/*
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* Initialize the EPROM handler.
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*/
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int eprom_init(struct hfi1_devdata *dd)
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{
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int ret = 0;
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/* only the discrete chip has an EPROM, nothing to do */
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if (dd->pcidev->device != PCI_DEVICE_ID_INTEL0)
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return 0;
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/* lock against other callers */
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mutex_lock(&eprom_mutex);
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if (eprom_available) /* already initialized */
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goto done_asic;
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/*
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* Lock against the other HFI on another OS - the mutex above
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* would have caught anything in this driver. It is OK if
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* both OSes reset the EPROM - as long as they don't do it at
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* the same time.
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*/
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ret = acquire_hw_mutex(dd);
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if (ret) {
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dd_dev_err(dd,
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"%s: unable to acquire hw mutex, no EPROM support\n",
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__func__);
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goto done_asic;
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}
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/* reset EPROM to be sure it is in a good state */
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/* set reset */
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write_csr(dd, ASIC_EEP_CTL_STAT,
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ASIC_EEP_CTL_STAT_EP_RESET_SMASK);
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/* clear reset, set speed */
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write_csr(dd, ASIC_EEP_CTL_STAT,
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EP_SPEED_FULL << ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT);
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/* wake the device with command "release powerdown NoID" */
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID);
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eprom_available = 1;
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release_hw_mutex(dd);
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done_asic:
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mutex_unlock(&eprom_mutex);
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return ret;
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}
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