![Linus Torvalds](/assets/img/avatar_default.png)
entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJS4WZPAAoJEDqPOy9afJhJVz4QAL63xispjEVuABUjgskR1fyo 7QljpqUJCOViqiVqNi1sPtM0irvfrApNwTpK3mGm20/kbNIBSdqGc/fI5CbWxXAU scRqplTTLY6F7nXJXGgiM/e5b31Tb+KmY9Su5chq1Yv6py4/yb6SzoohcBlQJ5in JKIxgLqe1VqUkCY2EFlqLwYqUtgr/Zm6ZJDt4LTwxc43apwgG7USMAS8ppx7nTgd oGgcsU4dNur1L4+ahvwqC+ntfoZNmVKJm+eY+JrHXJ2sga4PLaJcorgK2NXFpgln nwZQzRfbZLg7vNg/ODIDvP94mhc266xq2TCWzD/kMOBwmhsM0lySpzI/IM8qv1U2 Tdy9EHAj2iHoU+s1yPEUtNRV4h2+BGUUy54690XO30+VCLVEJUCC2KopDAk0G3ua qxSCb1mJto8EEq3jCJwKZSOUI7gcizDjHAaqfLlnDytMlsFJR7AJVj5IcRdgC/9s Vg975Xklkn33fWEuYQzdQdcmJ8ZCnydo92R2S0CaMgxMZqp2eoYZXJWvgCAvfQYC HjAtnBpHxNsZQeASvclb9bQrEisAUjIrxvuzLenQhg88WhBuyUDgBdretCzHFhP4 i62QGAhSYiNJJQzs+U9EndG6fRr/p98Pmw2pBAAn8UYOT2wWMj8wpR+IVT50Bmdi j6LsDpvc7CE2a4f+KoCa =Hh66 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
207 lines
5.8 KiB
C
207 lines
5.8 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/export.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include "clk.h"
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static u8 clk_periph_get_parent(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *mux_ops = periph->mux_ops;
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struct clk_hw *mux_hw = &periph->mux.hw;
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mux_hw->clk = hw->clk;
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return mux_ops->get_parent(mux_hw);
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}
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static int clk_periph_set_parent(struct clk_hw *hw, u8 index)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *mux_ops = periph->mux_ops;
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struct clk_hw *mux_hw = &periph->mux.hw;
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mux_hw->clk = hw->clk;
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return mux_ops->set_parent(mux_hw, index);
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}
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static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *div_ops = periph->div_ops;
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struct clk_hw *div_hw = &periph->divider.hw;
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div_hw->clk = hw->clk;
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return div_ops->recalc_rate(div_hw, parent_rate);
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}
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static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *div_ops = periph->div_ops;
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struct clk_hw *div_hw = &periph->divider.hw;
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div_hw->clk = hw->clk;
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return div_ops->round_rate(div_hw, rate, prate);
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}
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static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *div_ops = periph->div_ops;
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struct clk_hw *div_hw = &periph->divider.hw;
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div_hw->clk = hw->clk;
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return div_ops->set_rate(div_hw, rate, parent_rate);
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}
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static int clk_periph_is_enabled(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *gate_ops = periph->gate_ops;
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struct clk_hw *gate_hw = &periph->gate.hw;
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gate_hw->clk = hw->clk;
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return gate_ops->is_enabled(gate_hw);
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}
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static int clk_periph_enable(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *gate_ops = periph->gate_ops;
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struct clk_hw *gate_hw = &periph->gate.hw;
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gate_hw->clk = hw->clk;
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return gate_ops->enable(gate_hw);
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}
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static void clk_periph_disable(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *gate_ops = periph->gate_ops;
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struct clk_hw *gate_hw = &periph->gate.hw;
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gate_ops->disable(gate_hw);
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}
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const struct clk_ops tegra_clk_periph_ops = {
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.get_parent = clk_periph_get_parent,
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.set_parent = clk_periph_set_parent,
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.recalc_rate = clk_periph_recalc_rate,
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.round_rate = clk_periph_round_rate,
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.set_rate = clk_periph_set_rate,
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.is_enabled = clk_periph_is_enabled,
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.enable = clk_periph_enable,
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.disable = clk_periph_disable,
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};
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static const struct clk_ops tegra_clk_periph_nodiv_ops = {
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.get_parent = clk_periph_get_parent,
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.set_parent = clk_periph_set_parent,
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.is_enabled = clk_periph_is_enabled,
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.enable = clk_periph_enable,
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.disable = clk_periph_disable,
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};
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const struct clk_ops tegra_clk_periph_no_gate_ops = {
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.get_parent = clk_periph_get_parent,
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.set_parent = clk_periph_set_parent,
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.recalc_rate = clk_periph_recalc_rate,
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.round_rate = clk_periph_round_rate,
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.set_rate = clk_periph_set_rate,
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};
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static struct clk *_tegra_clk_register_periph(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph,
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void __iomem *clk_base, u32 offset,
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unsigned long flags)
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{
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struct clk *clk;
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struct clk_init_data init;
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struct tegra_clk_periph_regs *bank;
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bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);
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if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {
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flags |= CLK_SET_RATE_PARENT;
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init.ops = &tegra_clk_periph_nodiv_ops;
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} else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE)
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init.ops = &tegra_clk_periph_no_gate_ops;
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else
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init.ops = &tegra_clk_periph_ops;
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init.name = name;
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init.flags = flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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bank = get_reg_bank(periph->gate.clk_num);
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if (!bank)
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return ERR_PTR(-EINVAL);
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/* Data in .init is copied by clk_register(), so stack variable OK */
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periph->hw.init = &init;
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periph->magic = TEGRA_CLK_PERIPH_MAGIC;
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periph->mux.reg = clk_base + offset;
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periph->divider.reg = div ? (clk_base + offset) : NULL;
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periph->gate.clk_base = clk_base;
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periph->gate.regs = bank;
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periph->gate.enable_refcnt = periph_clk_enb_refcnt;
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clk = clk_register(NULL, &periph->hw);
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if (IS_ERR(clk))
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return clk;
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periph->mux.hw.clk = clk;
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periph->divider.hw.clk = div ? clk : NULL;
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periph->gate.hw.clk = clk;
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return clk;
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}
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struct clk *tegra_clk_register_periph(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset, unsigned long flags)
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{
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return _tegra_clk_register_periph(name, parent_names, num_parents,
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periph, clk_base, offset, flags);
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}
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struct clk *tegra_clk_register_periph_nodiv(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset)
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{
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periph->gate.flags |= TEGRA_PERIPH_NO_DIV;
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return _tegra_clk_register_periph(name, parent_names, num_parents,
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periph, clk_base, offset, CLK_SET_RATE_PARENT);
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}
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