![Artem Bityutskiy](/assets/img/avatar_default.png)
Be a bit stricter and add few more 'const' qualifiers. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
268 lines
6.8 KiB
C
268 lines
6.8 KiB
C
/*
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* drivers/mtd/maps/intel_vr_nor.c
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*
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* An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
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* Vermilion Range chipset.
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*
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* The Vermilion Range Expansion Bus supports four chip selects, each of which
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* has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
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* is a 256MiB memory region containing the address spaces for all four of the
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* chip selects, with start addresses hardcoded on 64MiB boundaries.
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*
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* This map driver only supports NOR flash on chip select 0. The buswidth
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* (either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
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* and Control Register for Chip Select 0 (EXP_TIMING_CS0). This driver does
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* not modify the value in the EXP_TIMING_CS0 register except to enable writing
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* and disable boot acceleration. The timing parameters in the register are
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* assumed to have been properly initialized by the BIOS. The reset default
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* timing parameters are maximally conservative (slow), so access to the flash
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* will be slower than it should be if the BIOS has not initialized the timing
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* parameters.
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*
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* Author: Andy Lowe <alowe@mvista.com>
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*
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* 2006 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/cfi.h>
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#include <linux/mtd/flashchip.h>
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#define DRV_NAME "vr_nor"
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struct vr_nor_mtd {
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void __iomem *csr_base;
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struct map_info map;
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struct mtd_info *info;
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struct pci_dev *dev;
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};
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/* Expansion Bus Configuration and Status Registers are in BAR 0 */
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#define EXP_CSR_MBAR 0
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/* Expansion Bus Memory Window is BAR 1 */
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#define EXP_WIN_MBAR 1
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/* Maximum address space for Chip Select 0 is 64MiB */
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#define CS0_SIZE 0x04000000
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/* Chip Select 0 is at offset 0 in the Memory Window */
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#define CS0_START 0x0
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/* Chip Select 0 Timing Register is at offset 0 in CSR */
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#define EXP_TIMING_CS0 0x00
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#define TIMING_CS_EN (1 << 31) /* Chip Select Enable */
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#define TIMING_BOOT_ACCEL_DIS (1 << 8) /* Boot Acceleration Disable */
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#define TIMING_WR_EN (1 << 1) /* Write Enable */
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#define TIMING_BYTE_EN (1 << 0) /* 8-bit vs 16-bit bus */
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#define TIMING_MASK 0x3FFF0000
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static void vr_nor_destroy_partitions(struct vr_nor_mtd *p)
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{
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mtd_device_unregister(p->info);
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}
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static int vr_nor_init_partitions(struct vr_nor_mtd *p)
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{
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/* register the flash bank */
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/* partition the flash bank */
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return mtd_device_parse_register(p->info, NULL, NULL, NULL, 0);
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}
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static void vr_nor_destroy_mtd_setup(struct vr_nor_mtd *p)
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{
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map_destroy(p->info);
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}
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static int vr_nor_mtd_setup(struct vr_nor_mtd *p)
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{
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static const char * const probe_types[] =
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{ "cfi_probe", "jedec_probe", NULL };
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const char * const *type;
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for (type = probe_types; !p->info && *type; type++)
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p->info = do_map_probe(*type, &p->map);
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if (!p->info)
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return -ENODEV;
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p->info->owner = THIS_MODULE;
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return 0;
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}
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static void vr_nor_destroy_maps(struct vr_nor_mtd *p)
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{
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unsigned int exp_timing_cs0;
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/* write-protect the flash bank */
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exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
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exp_timing_cs0 &= ~TIMING_WR_EN;
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writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
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/* unmap the flash window */
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iounmap(p->map.virt);
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/* unmap the csr window */
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iounmap(p->csr_base);
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}
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/*
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* Initialize the map_info structure and map the flash.
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* Returns 0 on success, nonzero otherwise.
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*/
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static int vr_nor_init_maps(struct vr_nor_mtd *p)
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{
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unsigned long csr_phys, csr_len;
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unsigned long win_phys, win_len;
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unsigned int exp_timing_cs0;
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int err;
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csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR);
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csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR);
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win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR);
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win_len = pci_resource_len(p->dev, EXP_WIN_MBAR);
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if (!csr_phys || !csr_len || !win_phys || !win_len)
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return -ENODEV;
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if (win_len < (CS0_START + CS0_SIZE))
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return -ENXIO;
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p->csr_base = ioremap_nocache(csr_phys, csr_len);
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if (!p->csr_base)
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return -ENOMEM;
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exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
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if (!(exp_timing_cs0 & TIMING_CS_EN)) {
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dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
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"is disabled.\n");
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err = -ENODEV;
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goto release;
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}
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if ((exp_timing_cs0 & TIMING_MASK) == TIMING_MASK) {
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dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
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"is configured for maximally slow access times.\n");
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}
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p->map.name = DRV_NAME;
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p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2;
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p->map.phys = win_phys + CS0_START;
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p->map.size = CS0_SIZE;
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p->map.virt = ioremap_nocache(p->map.phys, p->map.size);
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if (!p->map.virt) {
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err = -ENOMEM;
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goto release;
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}
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simple_map_init(&p->map);
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/* Enable writes to flash bank */
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exp_timing_cs0 |= TIMING_BOOT_ACCEL_DIS | TIMING_WR_EN;
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writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
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return 0;
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release:
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iounmap(p->csr_base);
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return err;
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}
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static struct pci_device_id vr_nor_pci_ids[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x500D)},
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{0,}
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};
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static void vr_nor_pci_remove(struct pci_dev *dev)
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{
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struct vr_nor_mtd *p = pci_get_drvdata(dev);
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pci_set_drvdata(dev, NULL);
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vr_nor_destroy_partitions(p);
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vr_nor_destroy_mtd_setup(p);
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vr_nor_destroy_maps(p);
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kfree(p);
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pci_release_regions(dev);
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pci_disable_device(dev);
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}
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static int vr_nor_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct vr_nor_mtd *p = NULL;
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unsigned int exp_timing_cs0;
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int err;
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err = pci_enable_device(dev);
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if (err)
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goto out;
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err = pci_request_regions(dev, DRV_NAME);
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if (err)
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goto disable_dev;
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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err = -ENOMEM;
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if (!p)
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goto release;
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p->dev = dev;
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err = vr_nor_init_maps(p);
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if (err)
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goto release;
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err = vr_nor_mtd_setup(p);
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if (err)
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goto destroy_maps;
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err = vr_nor_init_partitions(p);
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if (err)
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goto destroy_mtd_setup;
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pci_set_drvdata(dev, p);
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return 0;
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destroy_mtd_setup:
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map_destroy(p->info);
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destroy_maps:
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/* write-protect the flash bank */
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exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
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exp_timing_cs0 &= ~TIMING_WR_EN;
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writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
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/* unmap the flash window */
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iounmap(p->map.virt);
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/* unmap the csr window */
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iounmap(p->csr_base);
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release:
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kfree(p);
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pci_release_regions(dev);
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disable_dev:
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pci_disable_device(dev);
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out:
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return err;
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}
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static struct pci_driver vr_nor_pci_driver = {
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.name = DRV_NAME,
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.probe = vr_nor_pci_probe,
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.remove = vr_nor_pci_remove,
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.id_table = vr_nor_pci_ids,
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};
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module_pci_driver(vr_nor_pci_driver);
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MODULE_AUTHOR("Andy Lowe");
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MODULE_DESCRIPTION("MTD map driver for NOR flash on Intel Vermilion Range");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, vr_nor_pci_ids);
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