![Laurent Pinchart](/assets/img/avatar_default.png)
When a GPIO is handled by a separate driver the pinmux gpio_set_direction() handler won't be called. The pin mux type then need to be configured to GPIO at request time. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
475 lines
12 KiB
C
475 lines
12 KiB
C
/*
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* SuperH Pin Function Controller pinmux support.
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*
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* Copyright (C) 2012 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define DRV_NAME "sh-pfc"
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "core.h"
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#include "../core.h"
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#include "../pinconf.h"
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struct sh_pfc_pin_config {
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u32 type;
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};
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struct sh_pfc_pinctrl {
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struct pinctrl_dev *pctl;
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struct pinctrl_desc pctl_desc;
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struct sh_pfc *pfc;
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struct pinctrl_pin_desc *pins;
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struct sh_pfc_pin_config *configs;
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};
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static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->pfc->info->nr_groups;
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}
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static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->pfc->info->groups[selector].name;
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}
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static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
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const unsigned **pins, unsigned *num_pins)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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*pins = pmx->pfc->info->groups[selector].pins;
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*num_pins = pmx->pfc->info->groups[selector].nr_pins;
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return 0;
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}
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static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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unsigned offset)
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{
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seq_printf(s, "%s", DRV_NAME);
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}
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static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
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.get_groups_count = sh_pfc_get_groups_count,
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.get_group_name = sh_pfc_get_group_name,
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.get_group_pins = sh_pfc_get_group_pins,
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.pin_dbg_show = sh_pfc_pin_dbg_show,
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};
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static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->pfc->info->nr_functions;
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}
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static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->pfc->info->functions[selector].name;
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}
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static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned selector,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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*groups = pmx->pfc->info->functions[selector].groups;
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*num_groups = pmx->pfc->info->functions[selector].nr_groups;
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return 0;
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}
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static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
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unsigned group)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
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unsigned long flags;
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unsigned int i;
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int ret = 0;
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spin_lock_irqsave(&pfc->lock, flags);
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for (i = 0; i < grp->nr_pins; ++i) {
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int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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if (cfg->type != PINMUX_TYPE_NONE) {
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ret = -EBUSY;
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goto done;
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}
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}
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for (i = 0; i < grp->nr_pins; ++i) {
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ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
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if (ret < 0)
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break;
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}
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done:
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spin_unlock_irqrestore(&pfc->lock, flags);
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return ret;
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}
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static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
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unsigned group)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
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unsigned long flags;
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unsigned int i;
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spin_lock_irqsave(&pfc->lock, flags);
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for (i = 0; i < grp->nr_pins; ++i) {
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int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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cfg->type = PINMUX_TYPE_NONE;
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}
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spin_unlock_irqrestore(&pfc->lock, flags);
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}
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static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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int idx = sh_pfc_get_pin_index(pfc, offset);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&pfc->lock, flags);
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if (cfg->type != PINMUX_TYPE_NONE) {
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dev_err(pfc->dev,
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"Pin %u is busy, can't configure it as GPIO.\n",
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offset);
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ret = -EBUSY;
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goto done;
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}
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if (!pfc->gpio) {
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/* If GPIOs are handled externally the pin mux type need to be
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* set to GPIO here.
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*/
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
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if (ret < 0)
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goto done;
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}
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cfg->type = PINMUX_TYPE_GPIO;
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ret = 0;
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done:
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spin_unlock_irqrestore(&pfc->lock, flags);
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return ret;
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}
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static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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int idx = sh_pfc_get_pin_index(pfc, offset);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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unsigned long flags;
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spin_lock_irqsave(&pfc->lock, flags);
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cfg->type = PINMUX_TYPE_NONE;
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spin_unlock_irqrestore(&pfc->lock, flags);
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}
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static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset, bool input)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
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int idx = sh_pfc_get_pin_index(pfc, offset);
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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unsigned long flags;
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unsigned int dir;
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int ret;
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/* Check if the requested direction is supported by the pin. Not all SoC
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* provide pin config data, so perform the check conditionally.
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*/
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if (pin->configs) {
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dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
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if (!(pin->configs & dir))
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return -EINVAL;
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}
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spin_lock_irqsave(&pfc->lock, flags);
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ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
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if (ret < 0)
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goto done;
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cfg->type = new_type;
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done:
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spin_unlock_irqrestore(&pfc->lock, flags);
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return ret;
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}
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static const struct pinmux_ops sh_pfc_pinmux_ops = {
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.get_functions_count = sh_pfc_get_functions_count,
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.get_function_name = sh_pfc_get_function_name,
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.get_function_groups = sh_pfc_get_function_groups,
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.enable = sh_pfc_func_enable,
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.disable = sh_pfc_func_disable,
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.gpio_request_enable = sh_pfc_gpio_request_enable,
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.gpio_disable_free = sh_pfc_gpio_disable_free,
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.gpio_set_direction = sh_pfc_gpio_set_direction,
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};
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/* Check whether the requested parameter is supported for a pin. */
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static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
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enum pin_config_param param)
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{
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int idx = sh_pfc_get_pin_index(pfc, _pin);
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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return true;
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case PIN_CONFIG_BIAS_PULL_UP:
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return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
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default:
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return false;
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}
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}
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static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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unsigned long *config)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned long flags;
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unsigned int bias;
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if (!sh_pfc_pinconf_validate(pfc, _pin, param))
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return -ENOTSUPP;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (!pfc->info->ops || !pfc->info->ops->get_bias)
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return -ENOTSUPP;
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spin_lock_irqsave(&pfc->lock, flags);
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bias = pfc->info->ops->get_bias(pfc, _pin);
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spin_unlock_irqrestore(&pfc->lock, flags);
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if (bias != param)
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return -EINVAL;
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*config = 0;
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
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unsigned long config)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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enum pin_config_param param = pinconf_to_config_param(config);
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unsigned long flags;
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if (!sh_pfc_pinconf_validate(pfc, _pin, param))
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return -ENOTSUPP;
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switch (param) {
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_DISABLE:
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if (!pfc->info->ops || !pfc->info->ops->set_bias)
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return -ENOTSUPP;
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spin_lock_irqsave(&pfc->lock, flags);
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pfc->info->ops->set_bias(pfc, _pin, param);
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spin_unlock_irqrestore(&pfc->lock, flags);
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
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unsigned long config)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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const unsigned int *pins;
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unsigned int num_pins;
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unsigned int i;
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pins = pmx->pfc->info->groups[group].pins;
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num_pins = pmx->pfc->info->groups[group].nr_pins;
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for (i = 0; i < num_pins; ++i)
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sh_pfc_pinconf_set(pctldev, pins[i], config);
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return 0;
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}
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static const struct pinconf_ops sh_pfc_pinconf_ops = {
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.is_generic = true,
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.pin_config_get = sh_pfc_pinconf_get,
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.pin_config_set = sh_pfc_pinconf_set,
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.pin_config_group_set = sh_pfc_pinconf_group_set,
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.pin_config_config_dbg_show = pinconf_generic_dump_config,
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};
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/* PFC ranges -> pinctrl pin descs */
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static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
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{
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const struct pinmux_range *ranges;
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struct pinmux_range def_range;
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unsigned int nr_ranges;
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unsigned int nr_pins;
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unsigned int i;
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if (pfc->info->ranges == NULL) {
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def_range.begin = 0;
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def_range.end = pfc->info->nr_pins - 1;
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ranges = &def_range;
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nr_ranges = 1;
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} else {
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ranges = pfc->info->ranges;
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nr_ranges = pfc->info->nr_ranges;
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}
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pmx->pins = devm_kzalloc(pfc->dev,
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sizeof(*pmx->pins) * pfc->info->nr_pins,
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GFP_KERNEL);
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if (unlikely(!pmx->pins))
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return -ENOMEM;
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pmx->configs = devm_kzalloc(pfc->dev,
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sizeof(*pmx->configs) * pfc->info->nr_pins,
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GFP_KERNEL);
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if (unlikely(!pmx->configs))
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return -ENOMEM;
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for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
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const struct pinmux_range *range = &ranges[i];
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unsigned int number;
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for (number = range->begin; number <= range->end;
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number++, nr_pins++) {
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struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
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struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
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const struct sh_pfc_pin *info =
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&pfc->info->pins[nr_pins];
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pin->number = number;
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pin->name = info->name;
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cfg->type = PINMUX_TYPE_NONE;
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}
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}
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pfc->nr_pins = ranges[nr_ranges-1].end + 1;
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return nr_ranges;
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}
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int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
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{
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struct sh_pfc_pinctrl *pmx;
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int nr_ranges;
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pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
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if (unlikely(!pmx))
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return -ENOMEM;
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pmx->pfc = pfc;
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pfc->pinctrl = pmx;
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nr_ranges = sh_pfc_map_pins(pfc, pmx);
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if (unlikely(nr_ranges < 0))
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return nr_ranges;
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pmx->pctl_desc.name = DRV_NAME;
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pmx->pctl_desc.owner = THIS_MODULE;
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pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
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pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
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pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
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pmx->pctl_desc.pins = pmx->pins;
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pmx->pctl_desc.npins = pfc->info->nr_pins;
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pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
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if (pmx->pctl == NULL)
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return -EINVAL;
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return 0;
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}
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int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
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{
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struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
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pinctrl_unregister(pmx->pctl);
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pfc->pinctrl = NULL;
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return 0;
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}
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