![Vignesh R](/assets/img/avatar_default.png)
Register layout of a typical TPCC_EVT_MUX_M_N register is such that the lowest numbered event is at the lowest byte address and highest numbered event at highest byte address. But TPCC_EVT_MUX_60_63 register layout is different, in that the lowest numbered event is at the highest address and highest numbered event is at the lowest address. Therefore, modify ti_am335x_xbar_write() to handle TPCC_EVT_MUX_60_63 register accordingly. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
479 lines
12 KiB
C
479 lines
12 KiB
C
/*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#define TI_XBAR_DRA7 0
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#define TI_XBAR_AM335X 1
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static const u32 ti_xbar_type[] = {
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[TI_XBAR_DRA7] = TI_XBAR_DRA7,
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[TI_XBAR_AM335X] = TI_XBAR_AM335X,
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};
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static const struct of_device_id ti_dma_xbar_match[] = {
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{
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.compatible = "ti,dra7-dma-crossbar",
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.data = &ti_xbar_type[TI_XBAR_DRA7],
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},
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{
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.compatible = "ti,am335x-edma-crossbar",
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.data = &ti_xbar_type[TI_XBAR_AM335X],
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},
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{},
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};
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/* Crossbar on AM335x/AM437x family */
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#define TI_AM335X_XBAR_LINES 64
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struct ti_am335x_xbar_data {
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void __iomem *iomem;
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struct dma_router dmarouter;
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u32 xbar_events; /* maximum number of events to select in xbar */
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u32 dma_requests; /* number of DMA requests on eDMA */
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};
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struct ti_am335x_xbar_map {
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u16 dma_line;
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u8 mux_val;
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};
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static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u8 val)
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{
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/*
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* TPCC_EVT_MUX_60_63 register layout is different than the
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* rest, in the sense, that event 63 is mapped to lowest byte
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* and event 60 is mapped to highest, handle it separately.
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*/
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if (event >= 60 && event <= 63)
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writeb_relaxed(val, iomem + (63 - event % 4));
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else
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writeb_relaxed(val, iomem + event);
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}
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static void ti_am335x_xbar_free(struct device *dev, void *route_data)
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{
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struct ti_am335x_xbar_data *xbar = dev_get_drvdata(dev);
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struct ti_am335x_xbar_map *map = route_data;
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dev_dbg(dev, "Unmapping XBAR event %u on channel %u\n",
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map->mux_val, map->dma_line);
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ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0);
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kfree(map);
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}
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static void *ti_am335x_xbar_route_allocate(struct of_phandle_args *dma_spec,
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struct of_dma *ofdma)
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{
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struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
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struct ti_am335x_xbar_data *xbar = platform_get_drvdata(pdev);
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struct ti_am335x_xbar_map *map;
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if (dma_spec->args_count != 3)
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return ERR_PTR(-EINVAL);
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if (dma_spec->args[2] >= xbar->xbar_events) {
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dev_err(&pdev->dev, "Invalid XBAR event number: %d\n",
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dma_spec->args[2]);
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return ERR_PTR(-EINVAL);
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}
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if (dma_spec->args[0] >= xbar->dma_requests) {
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dev_err(&pdev->dev, "Invalid DMA request line number: %d\n",
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dma_spec->args[0]);
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return ERR_PTR(-EINVAL);
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}
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/* The of_node_put() will be done in the core for the node */
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dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0);
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if (!dma_spec->np) {
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dev_err(&pdev->dev, "Can't get DMA master\n");
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return ERR_PTR(-EINVAL);
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}
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map = kzalloc(sizeof(*map), GFP_KERNEL);
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if (!map) {
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of_node_put(dma_spec->np);
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return ERR_PTR(-ENOMEM);
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}
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map->dma_line = (u16)dma_spec->args[0];
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map->mux_val = (u8)dma_spec->args[2];
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dma_spec->args[2] = 0;
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dma_spec->args_count = 2;
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dev_dbg(&pdev->dev, "Mapping XBAR event%u to DMA%u\n",
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map->mux_val, map->dma_line);
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ti_am335x_xbar_write(xbar->iomem, map->dma_line, map->mux_val);
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return map;
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}
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static const struct of_device_id ti_am335x_master_match[] = {
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{ .compatible = "ti,edma3-tpcc", },
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{},
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};
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static int ti_am335x_xbar_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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const struct of_device_id *match;
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struct device_node *dma_node;
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struct ti_am335x_xbar_data *xbar;
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struct resource *res;
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void __iomem *iomem;
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int i, ret;
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if (!node)
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return -ENODEV;
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xbar = devm_kzalloc(&pdev->dev, sizeof(*xbar), GFP_KERNEL);
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if (!xbar)
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return -ENOMEM;
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dma_node = of_parse_phandle(node, "dma-masters", 0);
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if (!dma_node) {
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dev_err(&pdev->dev, "Can't get DMA master node\n");
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return -ENODEV;
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}
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match = of_match_node(ti_am335x_master_match, dma_node);
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if (!match) {
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dev_err(&pdev->dev, "DMA master is not supported\n");
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of_node_put(dma_node);
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return -EINVAL;
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}
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if (of_property_read_u32(dma_node, "dma-requests",
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&xbar->dma_requests)) {
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dev_info(&pdev->dev,
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"Missing XBAR output information, using %u.\n",
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TI_AM335X_XBAR_LINES);
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xbar->dma_requests = TI_AM335X_XBAR_LINES;
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}
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of_node_put(dma_node);
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if (of_property_read_u32(node, "dma-requests", &xbar->xbar_events)) {
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dev_info(&pdev->dev,
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"Missing XBAR input information, using %u.\n",
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TI_AM335X_XBAR_LINES);
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xbar->xbar_events = TI_AM335X_XBAR_LINES;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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iomem = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(iomem))
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return PTR_ERR(iomem);
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xbar->iomem = iomem;
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xbar->dmarouter.dev = &pdev->dev;
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xbar->dmarouter.route_free = ti_am335x_xbar_free;
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platform_set_drvdata(pdev, xbar);
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/* Reset the crossbar */
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for (i = 0; i < xbar->dma_requests; i++)
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ti_am335x_xbar_write(xbar->iomem, i, 0);
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ret = of_dma_router_register(node, ti_am335x_xbar_route_allocate,
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&xbar->dmarouter);
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return ret;
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}
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/* Crossbar on DRA7xx family */
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#define TI_DRA7_XBAR_OUTPUTS 127
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#define TI_DRA7_XBAR_INPUTS 256
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struct ti_dra7_xbar_data {
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void __iomem *iomem;
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struct dma_router dmarouter;
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struct mutex mutex;
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unsigned long *dma_inuse;
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u16 safe_val; /* Value to rest the crossbar lines */
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u32 xbar_requests; /* number of DMA requests connected to XBAR */
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u32 dma_requests; /* number of DMA requests forwarded to DMA */
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u32 dma_offset;
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};
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struct ti_dra7_xbar_map {
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u16 xbar_in;
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int xbar_out;
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};
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static inline void ti_dra7_xbar_write(void __iomem *iomem, int xbar, u16 val)
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{
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writew_relaxed(val, iomem + (xbar * 2));
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}
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static void ti_dra7_xbar_free(struct device *dev, void *route_data)
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{
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struct ti_dra7_xbar_data *xbar = dev_get_drvdata(dev);
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struct ti_dra7_xbar_map *map = route_data;
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dev_dbg(dev, "Unmapping XBAR%u (was routed to %d)\n",
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map->xbar_in, map->xbar_out);
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ti_dra7_xbar_write(xbar->iomem, map->xbar_out, xbar->safe_val);
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mutex_lock(&xbar->mutex);
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clear_bit(map->xbar_out, xbar->dma_inuse);
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mutex_unlock(&xbar->mutex);
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kfree(map);
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}
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static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
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struct of_dma *ofdma)
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{
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struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
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struct ti_dra7_xbar_data *xbar = platform_get_drvdata(pdev);
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struct ti_dra7_xbar_map *map;
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if (dma_spec->args[0] >= xbar->xbar_requests) {
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dev_err(&pdev->dev, "Invalid XBAR request number: %d\n",
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dma_spec->args[0]);
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return ERR_PTR(-EINVAL);
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}
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/* The of_node_put() will be done in the core for the node */
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dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0);
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if (!dma_spec->np) {
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dev_err(&pdev->dev, "Can't get DMA master\n");
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return ERR_PTR(-EINVAL);
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}
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map = kzalloc(sizeof(*map), GFP_KERNEL);
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if (!map) {
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of_node_put(dma_spec->np);
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return ERR_PTR(-ENOMEM);
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}
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mutex_lock(&xbar->mutex);
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map->xbar_out = find_first_zero_bit(xbar->dma_inuse,
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xbar->dma_requests);
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if (map->xbar_out == xbar->dma_requests) {
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mutex_unlock(&xbar->mutex);
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dev_err(&pdev->dev, "Run out of free DMA requests\n");
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kfree(map);
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return ERR_PTR(-ENOMEM);
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}
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set_bit(map->xbar_out, xbar->dma_inuse);
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mutex_unlock(&xbar->mutex);
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map->xbar_in = (u16)dma_spec->args[0];
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dma_spec->args[0] = map->xbar_out + xbar->dma_offset;
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dev_dbg(&pdev->dev, "Mapping XBAR%u to DMA%d\n",
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map->xbar_in, map->xbar_out);
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ti_dra7_xbar_write(xbar->iomem, map->xbar_out, map->xbar_in);
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return map;
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}
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#define TI_XBAR_EDMA_OFFSET 0
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#define TI_XBAR_SDMA_OFFSET 1
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static const u32 ti_dma_offset[] = {
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[TI_XBAR_EDMA_OFFSET] = 0,
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[TI_XBAR_SDMA_OFFSET] = 1,
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};
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static const struct of_device_id ti_dra7_master_match[] = {
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{
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.compatible = "ti,omap4430-sdma",
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.data = &ti_dma_offset[TI_XBAR_SDMA_OFFSET],
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},
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{
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.compatible = "ti,edma3",
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.data = &ti_dma_offset[TI_XBAR_EDMA_OFFSET],
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},
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{
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.compatible = "ti,edma3-tpcc",
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.data = &ti_dma_offset[TI_XBAR_EDMA_OFFSET],
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},
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{},
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};
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static inline void ti_dra7_xbar_reserve(int offset, int len, unsigned long *p)
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{
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for (; len > 0; len--)
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set_bit(offset + (len - 1), p);
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}
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static int ti_dra7_xbar_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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const struct of_device_id *match;
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struct device_node *dma_node;
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struct ti_dra7_xbar_data *xbar;
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struct property *prop;
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struct resource *res;
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u32 safe_val;
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int sz;
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void __iomem *iomem;
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int i, ret;
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if (!node)
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return -ENODEV;
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xbar = devm_kzalloc(&pdev->dev, sizeof(*xbar), GFP_KERNEL);
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if (!xbar)
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return -ENOMEM;
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dma_node = of_parse_phandle(node, "dma-masters", 0);
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if (!dma_node) {
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dev_err(&pdev->dev, "Can't get DMA master node\n");
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return -ENODEV;
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}
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match = of_match_node(ti_dra7_master_match, dma_node);
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if (!match) {
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dev_err(&pdev->dev, "DMA master is not supported\n");
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of_node_put(dma_node);
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return -EINVAL;
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}
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if (of_property_read_u32(dma_node, "dma-requests",
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&xbar->dma_requests)) {
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dev_info(&pdev->dev,
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"Missing XBAR output information, using %u.\n",
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TI_DRA7_XBAR_OUTPUTS);
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xbar->dma_requests = TI_DRA7_XBAR_OUTPUTS;
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}
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of_node_put(dma_node);
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xbar->dma_inuse = devm_kcalloc(&pdev->dev,
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BITS_TO_LONGS(xbar->dma_requests),
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sizeof(unsigned long), GFP_KERNEL);
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if (!xbar->dma_inuse)
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return -ENOMEM;
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if (of_property_read_u32(node, "dma-requests", &xbar->xbar_requests)) {
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dev_info(&pdev->dev,
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"Missing XBAR input information, using %u.\n",
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TI_DRA7_XBAR_INPUTS);
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xbar->xbar_requests = TI_DRA7_XBAR_INPUTS;
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}
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if (!of_property_read_u32(node, "ti,dma-safe-map", &safe_val))
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xbar->safe_val = (u16)safe_val;
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prop = of_find_property(node, "ti,reserved-dma-request-ranges", &sz);
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if (prop) {
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const char pname[] = "ti,reserved-dma-request-ranges";
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u32 (*rsv_events)[2];
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size_t nelm = sz / sizeof(*rsv_events);
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int i;
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if (!nelm)
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return -EINVAL;
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rsv_events = kcalloc(nelm, sizeof(*rsv_events), GFP_KERNEL);
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if (!rsv_events)
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return -ENOMEM;
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ret = of_property_read_u32_array(node, pname, (u32 *)rsv_events,
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nelm * 2);
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if (ret)
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return ret;
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for (i = 0; i < nelm; i++) {
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ti_dra7_xbar_reserve(rsv_events[i][0], rsv_events[i][1],
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xbar->dma_inuse);
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}
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kfree(rsv_events);
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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iomem = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(iomem))
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return PTR_ERR(iomem);
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xbar->iomem = iomem;
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xbar->dmarouter.dev = &pdev->dev;
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xbar->dmarouter.route_free = ti_dra7_xbar_free;
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xbar->dma_offset = *(u32 *)match->data;
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mutex_init(&xbar->mutex);
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platform_set_drvdata(pdev, xbar);
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/* Reset the crossbar */
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for (i = 0; i < xbar->dma_requests; i++) {
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if (!test_bit(i, xbar->dma_inuse))
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ti_dra7_xbar_write(xbar->iomem, i, xbar->safe_val);
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}
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ret = of_dma_router_register(node, ti_dra7_xbar_route_allocate,
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&xbar->dmarouter);
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if (ret) {
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/* Restore the defaults for the crossbar */
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for (i = 0; i < xbar->dma_requests; i++) {
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if (!test_bit(i, xbar->dma_inuse))
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ti_dra7_xbar_write(xbar->iomem, i, i);
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}
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}
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return ret;
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}
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static int ti_dma_xbar_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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int ret;
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match = of_match_node(ti_dma_xbar_match, pdev->dev.of_node);
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if (unlikely(!match))
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return -EINVAL;
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switch (*(u32 *)match->data) {
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case TI_XBAR_DRA7:
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ret = ti_dra7_xbar_probe(pdev);
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break;
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case TI_XBAR_AM335X:
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ret = ti_am335x_xbar_probe(pdev);
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break;
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default:
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dev_err(&pdev->dev, "Unsupported crossbar\n");
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ret = -ENODEV;
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break;
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}
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return ret;
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}
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static struct platform_driver ti_dma_xbar_driver = {
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.driver = {
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.name = "ti-dma-crossbar",
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.of_match_table = of_match_ptr(ti_dma_xbar_match),
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},
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.probe = ti_dma_xbar_probe,
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};
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static int omap_dmaxbar_init(void)
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{
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return platform_driver_register(&ti_dma_xbar_driver);
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}
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arch_initcall(omap_dmaxbar_init);
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