cebfa85eb8
Pull MIPS updates from Ralf Baechle: "The MIPS bits for 3.8. This also includes a bunch fixes that were sitting in the linux-mips.org git tree for a long time. This pull request contains updates to several OCTEON drivers and the board support code for BCM47XX, BCM63XX, XLP, XLR, XLS, lantiq, Loongson1B, updates to the SSB bus support, MIPS kexec code and adds support for kdump. When pulling this, there are two expected merge conflicts in include/linux/bcma/bcma_driver_chipcommon.h which are trivial to resolve, just remove the conflict markers and keep both alternatives." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (90 commits) MIPS: PMC-Sierra Yosemite: Remove support. VIDEO: Newport Fix console crashes MIPS: wrppmc: Fix build of PCI code. MIPS: IP22/IP28: Fix build of EISA code. MIPS: RB532: Fix build of prom code. MIPS: PowerTV: Fix build. MIPS: IP27: Correct fucked grammar in ops-bridge.c MIPS: Highmem: Fix build error if CONFIG_DEBUG_HIGHMEM is disabled MIPS: Fix potencial corruption MIPS: Fix for warning from FPU emulation code MIPS: Handle COP3 Unusable exception as COP1X for FP emulation MIPS: Fix poweroff failure when HOTPLUG_CPU configured. MIPS: MT: Fix build with CONFIG_UIDGID_STRICT_TYPE_CHECKS=y MIPS: Remove unused smvp.h MIPS/EDAC: Improve OCTEON EDAC support. MIPS: OCTEON: Add definitions for OCTEON memory contoller registers. MIPS: OCTEON: Add OCTEON family definitions to octeon-model.h ata: pata_octeon_cf: Use correct byte order for DMA in when built little-endian. MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree. MIPS: Remove usage of CEVT_R4K_LIB config option. ...
345 lines
8.5 KiB
C
345 lines
8.5 KiB
C
/*
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* Broadcom specific AMBA
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* ChipCommon core driver
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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* Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcm47xx_wdt.h>
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#include <linux/export.h>
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#include <linux/platform_device.h>
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#include <linux/bcma/bcma.h>
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static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
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u32 mask, u32 value)
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{
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value &= mask;
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value |= bcma_cc_read32(cc, offset) & ~mask;
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bcma_cc_write32(cc, offset, value);
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return value;
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}
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static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
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{
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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return bcma_pmu_get_alp_clock(cc);
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return 20000000;
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}
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static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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u32 nb;
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if (cc->capabilities & BCMA_CC_CAP_PMU) {
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if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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nb = 32;
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else if (cc->core->id.rev < 26)
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nb = 16;
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else
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nb = (cc->core->id.rev >= 37) ? 32 : 24;
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} else {
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nb = 28;
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}
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if (nb == 32)
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return 0xffffffff;
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else
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return (1 << nb) - 1;
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}
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static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
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u32 ticks)
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{
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struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
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return bcma_chipco_watchdog_timer_set(cc, ticks);
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}
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static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
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u32 ms)
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{
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struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
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u32 ticks;
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ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
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return ticks / cc->ticks_per_ms;
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}
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static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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if (cc->capabilities & BCMA_CC_CAP_PMU) {
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if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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/* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
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return bcma_chipco_get_alp_clock(cc) / 4000;
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else
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/* based on 32KHz ILP clock */
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return 32;
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} else {
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return bcma_chipco_get_alp_clock(cc) / 1000;
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}
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}
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int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
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{
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struct bcm47xx_wdt wdt = {};
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struct platform_device *pdev;
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wdt.driver_data = cc;
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wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
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wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
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wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
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pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
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cc->core->bus->num, &wdt,
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sizeof(wdt));
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if (IS_ERR(pdev))
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return PTR_ERR(pdev);
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cc->watchdog = pdev;
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return 0;
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}
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void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
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{
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if (cc->early_setup_done)
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return;
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spin_lock_init(&cc->gpio_lock);
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if (cc->core->id.rev >= 11)
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cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
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if (cc->core->id.rev >= 35)
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cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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bcma_pmu_early_init(cc);
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cc->early_setup_done = true;
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}
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void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
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{
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u32 leddc_on = 10;
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u32 leddc_off = 90;
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if (cc->setup_done)
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return;
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bcma_core_chipcommon_early_init(cc);
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if (cc->core->id.rev >= 20) {
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bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
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bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
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}
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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bcma_pmu_init(cc);
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if (cc->capabilities & BCMA_CC_CAP_PCTL)
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bcma_err(cc->core->bus, "Power control not implemented!\n");
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if (cc->core->id.rev >= 16) {
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if (cc->core->bus->sprom.leddc_on_time &&
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cc->core->bus->sprom.leddc_off_time) {
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leddc_on = cc->core->bus->sprom.leddc_on_time;
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leddc_off = cc->core->bus->sprom.leddc_off_time;
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}
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bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
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((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
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(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
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}
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cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
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cc->setup_done = true;
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}
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
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{
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u32 maxt;
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enum bcma_clkmode clkmode;
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maxt = bcma_chipco_watchdog_get_max_timer(cc);
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if (cc->capabilities & BCMA_CC_CAP_PMU) {
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if (ticks == 1)
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ticks = 2;
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else if (ticks > maxt)
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ticks = maxt;
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bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
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} else {
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clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
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bcma_core_set_clockmode(cc->core, clkmode);
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if (ticks > maxt)
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ticks = maxt;
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/* instant NMI */
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bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
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}
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return ticks;
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}
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
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}
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u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
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{
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return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
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}
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u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
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{
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return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
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}
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u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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unsigned long flags;
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u32 res;
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spin_lock_irqsave(&cc->gpio_lock, flags);
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res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
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spin_unlock_irqrestore(&cc->gpio_lock, flags);
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return res;
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}
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u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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unsigned long flags;
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u32 res;
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spin_lock_irqsave(&cc->gpio_lock, flags);
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res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
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spin_unlock_irqrestore(&cc->gpio_lock, flags);
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return res;
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}
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/*
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* If the bit is set to 0, chipcommon controlls this GPIO,
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* if the bit is set to 1, it is used by some part of the chip and not our code.
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*/
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u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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unsigned long flags;
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u32 res;
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spin_lock_irqsave(&cc->gpio_lock, flags);
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res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
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spin_unlock_irqrestore(&cc->gpio_lock, flags);
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return res;
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
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u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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unsigned long flags;
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u32 res;
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spin_lock_irqsave(&cc->gpio_lock, flags);
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res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
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spin_unlock_irqrestore(&cc->gpio_lock, flags);
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return res;
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}
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u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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unsigned long flags;
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u32 res;
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spin_lock_irqsave(&cc->gpio_lock, flags);
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res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
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spin_unlock_irqrestore(&cc->gpio_lock, flags);
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return res;
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}
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u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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unsigned long flags;
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u32 res;
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if (cc->core->id.rev < 20)
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return 0;
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spin_lock_irqsave(&cc->gpio_lock, flags);
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res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
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spin_unlock_irqrestore(&cc->gpio_lock, flags);
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return res;
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}
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u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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unsigned long flags;
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u32 res;
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if (cc->core->id.rev < 20)
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return 0;
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spin_lock_irqsave(&cc->gpio_lock, flags);
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res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
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spin_unlock_irqrestore(&cc->gpio_lock, flags);
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return res;
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}
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
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{
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unsigned int irq;
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u32 baud_base;
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u32 i;
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unsigned int ccrev = cc->core->id.rev;
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struct bcma_serial_port *ports = cc->serial_ports;
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if (ccrev >= 11 && ccrev != 15) {
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baud_base = bcma_chipco_get_alp_clock(cc);
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if (ccrev >= 21) {
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/* Turn off UART clock before switching clocksource. */
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bcma_cc_write32(cc, BCMA_CC_CORECTL,
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bcma_cc_read32(cc, BCMA_CC_CORECTL)
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& ~BCMA_CC_CORECTL_UARTCLKEN);
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}
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/* Set the override bit so we don't divide it */
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bcma_cc_write32(cc, BCMA_CC_CORECTL,
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bcma_cc_read32(cc, BCMA_CC_CORECTL)
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| BCMA_CC_CORECTL_UARTCLK0);
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if (ccrev >= 21) {
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/* Re-enable the UART clock. */
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bcma_cc_write32(cc, BCMA_CC_CORECTL,
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bcma_cc_read32(cc, BCMA_CC_CORECTL)
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| BCMA_CC_CORECTL_UARTCLKEN);
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}
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} else {
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bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
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return;
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}
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irq = bcma_core_mips_irq(cc->core);
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/* Determine the registers of the UARTs */
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cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
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for (i = 0; i < cc->nr_serial_ports; i++) {
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ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
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(i * 256);
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ports[i].irq = irq;
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ports[i].baud_base = baud_base;
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ports[i].reg_shift = 0;
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}
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}
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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