7801bbe1bd
The CP0_EBase register is a standard feature of MIPS32r2, so we should always have been implementing it properly. However the register value was ignored and wasn't exposed to userland. Fix the emulation of exceptions and interrupts to use the value stored in guest CP0_EBase, and fix the masks so that the top 3 bits (rather than the standard 2) are fixed, so that it is always in the guest KSeg0 segment. Also add CP0_EBASE to the KVM one_reg interface so it can be accessed by userland, also allowing the CPU number field to be written (which isn't permitted by the guest). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
243 lines
5.8 KiB
C
243 lines
5.8 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* KVM/MIPS: Interrupt delivery
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/vmalloc.h>
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#include <linux/fs.h>
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#include <linux/bootmem.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include <linux/kvm_host.h>
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#include "interrupt.h"
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void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
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{
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set_bit(priority, &vcpu->arch.pending_exceptions);
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}
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void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
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{
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clear_bit(priority, &vcpu->arch.pending_exceptions);
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}
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void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu)
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{
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/*
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* Cause bits to reflect the pending timer interrupt,
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* the EXC code will be set when we are actually
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* delivering the interrupt:
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*/
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kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 | C_TI));
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/* Queue up an INT exception for the core */
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kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
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}
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void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu)
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{
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kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 | C_TI));
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kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_TIMER);
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}
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void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
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struct kvm_mips_interrupt *irq)
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{
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int intr = (int)irq->irq;
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/*
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* Cause bits to reflect the pending IO interrupt,
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* the EXC code will be set when we are actually
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* delivering the interrupt:
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*/
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switch (intr) {
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case 2:
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kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0));
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/* Queue up an INT exception for the core */
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kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IO);
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break;
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case 3:
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kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1));
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kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IPI_1);
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break;
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case 4:
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kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2));
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kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IPI_2);
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break;
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default:
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break;
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}
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}
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void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
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struct kvm_mips_interrupt *irq)
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{
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int intr = (int)irq->irq;
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switch (intr) {
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case -2:
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kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0));
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kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IO);
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break;
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case -3:
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kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1));
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kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_1);
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break;
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case -4:
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kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2));
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kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_2);
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break;
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default:
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break;
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}
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}
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/* Deliver the interrupt of the corresponding priority, if possible. */
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int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
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u32 cause)
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{
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int allowed = 0;
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u32 exccode;
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struct kvm_vcpu_arch *arch = &vcpu->arch;
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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switch (priority) {
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case MIPS_EXC_INT_TIMER:
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if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
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&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
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&& (kvm_read_c0_guest_status(cop0) & IE_IRQ5)) {
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allowed = 1;
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exccode = EXCCODE_INT;
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}
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break;
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case MIPS_EXC_INT_IO:
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if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
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&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
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&& (kvm_read_c0_guest_status(cop0) & IE_IRQ0)) {
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allowed = 1;
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exccode = EXCCODE_INT;
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}
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break;
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case MIPS_EXC_INT_IPI_1:
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if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
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&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
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&& (kvm_read_c0_guest_status(cop0) & IE_IRQ1)) {
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allowed = 1;
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exccode = EXCCODE_INT;
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}
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break;
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case MIPS_EXC_INT_IPI_2:
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if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
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&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
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&& (kvm_read_c0_guest_status(cop0) & IE_IRQ2)) {
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allowed = 1;
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exccode = EXCCODE_INT;
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}
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break;
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default:
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break;
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}
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/* Are we allowed to deliver the interrupt ??? */
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if (allowed) {
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if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
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/* save old pc */
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kvm_write_c0_guest_epc(cop0, arch->pc);
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kvm_set_c0_guest_status(cop0, ST0_EXL);
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if (cause & CAUSEF_BD)
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kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
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else
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kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
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kvm_debug("Delivering INT @ pc %#lx\n", arch->pc);
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} else
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kvm_err("Trying to deliver interrupt when EXL is already set\n");
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kvm_change_c0_guest_cause(cop0, CAUSEF_EXCCODE,
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(exccode << CAUSEB_EXCCODE));
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/* XXXSL Set PC to the interrupt exception entry point */
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arch->pc = kvm_mips_guest_exception_base(vcpu);
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if (kvm_read_c0_guest_cause(cop0) & CAUSEF_IV)
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arch->pc += 0x200;
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else
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arch->pc += 0x180;
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clear_bit(priority, &vcpu->arch.pending_exceptions);
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}
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return allowed;
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}
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int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
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u32 cause)
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{
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return 1;
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}
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void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause)
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{
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unsigned long *pending = &vcpu->arch.pending_exceptions;
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unsigned long *pending_clr = &vcpu->arch.pending_exceptions_clr;
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unsigned int priority;
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if (!(*pending) && !(*pending_clr))
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return;
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priority = __ffs(*pending_clr);
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while (priority <= MIPS_EXC_MAX) {
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if (kvm_mips_callbacks->irq_clear(vcpu, priority, cause)) {
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if (!KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE)
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break;
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}
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priority = find_next_bit(pending_clr,
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BITS_PER_BYTE * sizeof(*pending_clr),
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priority + 1);
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}
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priority = __ffs(*pending);
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while (priority <= MIPS_EXC_MAX) {
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if (kvm_mips_callbacks->irq_deliver(vcpu, priority, cause)) {
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if (!KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE)
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break;
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}
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priority = find_next_bit(pending,
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BITS_PER_BYTE * sizeof(*pending),
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priority + 1);
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}
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}
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int kvm_mips_pending_timer(struct kvm_vcpu *vcpu)
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{
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return test_bit(MIPS_EXC_INT_TIMER, &vcpu->arch.pending_exceptions);
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}
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