![Wei Yongjun](/assets/img/avatar_default.png)
In case of error, the function devm_ioremap_resource() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().
Fixes: 2fc305be36
("usb: chipidea: msm: Mux over secondary phy at the
right time")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
321 lines
7.5 KiB
C
321 lines
7.5 KiB
C
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/usb/chipidea.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/io.h>
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#include <linux/reset-controller.h>
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#include <linux/extcon.h>
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#include <linux/of.h>
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#include "ci.h"
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#define HS_PHY_AHB_MODE 0x0098
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#define HS_PHY_GENCONFIG 0x009c
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#define HS_PHY_TXFIFO_IDLE_FORCE_DIS BIT(4)
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#define HS_PHY_GENCONFIG_2 0x00a0
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#define HS_PHY_SESS_VLD_CTRL_EN BIT(7)
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#define HS_PHY_ULPI_TX_PKT_EN_CLR_FIX BIT(19)
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#define HSPHY_SESS_VLD_CTRL BIT(25)
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/* Vendor base starts at 0x200 beyond CI base */
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#define HS_PHY_CTRL 0x0040
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#define HS_PHY_SEC_CTRL 0x0078
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#define HS_PHY_DIG_CLAMP_N BIT(16)
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#define HS_PHY_POR_ASSERT BIT(0)
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struct ci_hdrc_msm {
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struct platform_device *ci;
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struct clk *core_clk;
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struct clk *iface_clk;
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struct clk *fs_clk;
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struct ci_hdrc_platform_data pdata;
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struct reset_controller_dev rcdev;
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bool secondary_phy;
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bool hsic;
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void __iomem *base;
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};
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static int
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ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id)
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{
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struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev);
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void __iomem *addr = ci_msm->base;
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u32 val;
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if (id)
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addr += HS_PHY_SEC_CTRL;
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else
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addr += HS_PHY_CTRL;
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val = readl_relaxed(addr);
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val |= HS_PHY_POR_ASSERT;
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writel(val, addr);
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/*
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* wait for minimum 10 microseconds as suggested by manual.
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* Use a slightly larger value since the exact value didn't
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* work 100% of the time.
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*/
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udelay(12);
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val &= ~HS_PHY_POR_ASSERT;
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writel(val, addr);
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return 0;
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}
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static const struct reset_control_ops ci_hdrc_msm_reset_ops = {
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.reset = ci_hdrc_msm_por_reset,
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};
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static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
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{
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struct device *dev = ci->dev->parent;
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struct ci_hdrc_msm *msm_ci = dev_get_drvdata(dev);
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int ret;
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switch (event) {
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case CI_HDRC_CONTROLLER_RESET_EVENT:
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dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");
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hw_phymode_configure(ci);
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if (msm_ci->secondary_phy) {
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u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL);
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val |= HS_PHY_DIG_CLAMP_N;
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writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL);
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}
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ret = phy_init(ci->phy);
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if (ret)
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return ret;
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ret = phy_power_on(ci->phy);
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if (ret) {
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phy_exit(ci->phy);
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return ret;
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}
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/* use AHB transactor, allow posted data writes */
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hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8);
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/* workaround for rx buffer collision issue */
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hw_write_id_reg(ci, HS_PHY_GENCONFIG,
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HS_PHY_TXFIFO_IDLE_FORCE_DIS, 0);
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if (!msm_ci->hsic)
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hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,
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HS_PHY_ULPI_TX_PKT_EN_CLR_FIX, 0);
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if (!IS_ERR(ci->platdata->vbus_extcon.edev)) {
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hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,
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HS_PHY_SESS_VLD_CTRL_EN,
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HS_PHY_SESS_VLD_CTRL_EN);
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hw_write(ci, OP_USBCMD, HSPHY_SESS_VLD_CTRL,
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HSPHY_SESS_VLD_CTRL);
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}
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break;
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case CI_HDRC_CONTROLLER_STOPPED_EVENT:
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dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
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phy_power_off(ci->phy);
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phy_exit(ci->phy);
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break;
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default:
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dev_dbg(dev, "unknown ci_hdrc event\n");
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break;
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}
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return 0;
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}
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static int ci_hdrc_msm_mux_phy(struct ci_hdrc_msm *ci,
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struct platform_device *pdev)
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{
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struct regmap *regmap;
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struct device *dev = &pdev->dev;
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struct of_phandle_args args;
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u32 val;
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int ret;
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ret = of_parse_phandle_with_fixed_args(dev->of_node, "phy-select", 2, 0,
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&args);
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if (ret)
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return 0;
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regmap = syscon_node_to_regmap(args.np);
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of_node_put(args.np);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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ret = regmap_write(regmap, args.args[0], args.args[1]);
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if (ret)
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return ret;
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ci->secondary_phy = !!args.args[1];
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if (ci->secondary_phy) {
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val = readl_relaxed(ci->base + HS_PHY_SEC_CTRL);
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val |= HS_PHY_DIG_CLAMP_N;
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writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL);
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}
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return 0;
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}
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static int ci_hdrc_msm_probe(struct platform_device *pdev)
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{
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struct ci_hdrc_msm *ci;
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struct platform_device *plat_ci;
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struct clk *clk;
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struct reset_control *reset;
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struct resource *res;
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int ret;
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struct device_node *ulpi_node, *phy_node;
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dev_dbg(&pdev->dev, "ci_hdrc_msm_probe\n");
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ci = devm_kzalloc(&pdev->dev, sizeof(*ci), GFP_KERNEL);
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if (!ci)
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return -ENOMEM;
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platform_set_drvdata(pdev, ci);
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ci->pdata.name = "ci_hdrc_msm";
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ci->pdata.capoffset = DEF_CAPOFFSET;
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ci->pdata.flags = CI_HDRC_REGS_SHARED | CI_HDRC_DISABLE_STREAMING |
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CI_HDRC_OVERRIDE_AHB_BURST |
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CI_HDRC_OVERRIDE_PHY_CONTROL;
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ci->pdata.notify_event = ci_hdrc_msm_notify_event;
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reset = devm_reset_control_get(&pdev->dev, "core");
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if (IS_ERR(reset))
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return PTR_ERR(reset);
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ci->core_clk = clk = devm_clk_get(&pdev->dev, "core");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ci->iface_clk = clk = devm_clk_get(&pdev->dev, "iface");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ci->fs_clk = clk = devm_clk_get(&pdev->dev, "fs");
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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ci->fs_clk = NULL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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ci->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(ci->base))
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return PTR_ERR(ci->base);
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ci->rcdev.owner = THIS_MODULE;
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ci->rcdev.ops = &ci_hdrc_msm_reset_ops;
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ci->rcdev.of_node = pdev->dev.of_node;
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ci->rcdev.nr_resets = 2;
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ret = reset_controller_register(&ci->rcdev);
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if (ret)
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return ret;
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ret = clk_prepare_enable(ci->fs_clk);
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if (ret)
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goto err_fs;
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reset_control_assert(reset);
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usleep_range(10000, 12000);
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reset_control_deassert(reset);
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clk_disable_unprepare(ci->fs_clk);
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ret = clk_prepare_enable(ci->core_clk);
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if (ret)
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goto err_fs;
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ret = clk_prepare_enable(ci->iface_clk);
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if (ret)
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goto err_iface;
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ret = ci_hdrc_msm_mux_phy(ci, pdev);
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if (ret)
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goto err_mux;
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ulpi_node = of_find_node_by_name(pdev->dev.of_node, "ulpi");
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if (ulpi_node) {
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phy_node = of_get_next_available_child(ulpi_node, NULL);
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ci->hsic = of_device_is_compatible(phy_node, "qcom,usb-hsic-phy");
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of_node_put(phy_node);
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}
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of_node_put(ulpi_node);
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plat_ci = ci_hdrc_add_device(&pdev->dev, pdev->resource,
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pdev->num_resources, &ci->pdata);
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if (IS_ERR(plat_ci)) {
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ret = PTR_ERR(plat_ci);
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if (ret != -EPROBE_DEFER)
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dev_err(&pdev->dev, "ci_hdrc_add_device failed!\n");
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goto err_mux;
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}
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ci->ci = plat_ci;
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_no_callbacks(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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return 0;
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err_mux:
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clk_disable_unprepare(ci->iface_clk);
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err_iface:
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clk_disable_unprepare(ci->core_clk);
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err_fs:
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reset_controller_unregister(&ci->rcdev);
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return ret;
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}
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static int ci_hdrc_msm_remove(struct platform_device *pdev)
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{
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struct ci_hdrc_msm *ci = platform_get_drvdata(pdev);
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pm_runtime_disable(&pdev->dev);
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ci_hdrc_remove_device(ci->ci);
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clk_disable_unprepare(ci->iface_clk);
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clk_disable_unprepare(ci->core_clk);
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reset_controller_unregister(&ci->rcdev);
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return 0;
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}
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static const struct of_device_id msm_ci_dt_match[] = {
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{ .compatible = "qcom,ci-hdrc", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, msm_ci_dt_match);
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static struct platform_driver ci_hdrc_msm_driver = {
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.probe = ci_hdrc_msm_probe,
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.remove = ci_hdrc_msm_remove,
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.driver = {
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.name = "msm_hsusb",
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.of_match_table = msm_ci_dt_match,
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},
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};
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module_platform_driver(ci_hdrc_msm_driver);
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MODULE_ALIAS("platform:msm_hsusb");
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MODULE_ALIAS("platform:ci13xxx_msm");
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MODULE_LICENSE("GPL v2");
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