![Russell King - ARM Linux](/assets/img/avatar_default.png)
Everyone deals with assigning DMA cookies in the same way (it's part of the API so they should be), so lets consolidate the common code into a helper function to avoid this duplication. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
837 lines
23 KiB
C
837 lines
23 KiB
C
/*
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* Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
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* Copyright (C) Semihalf 2009
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* Copyright (C) Ilya Yanok, Emcraft Systems 2010
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*
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* Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
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* (defines, structures and comments) was taken from MPC5121 DMA driver
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* written by Hongjun Chen <hong-jun.chen@freescale.com>.
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*
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* Approved as OSADL project by a majority of OSADL members and funded
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* by OSADL membership fees in 2009; for details see www.osadl.org.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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/*
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* This is initial version of MPC5121 DMA driver. Only memory to memory
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* transfers are supported (tested using dmatest module).
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*/
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#include <linux/module.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/random.h>
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#include "dmaengine.h"
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/* Number of DMA Transfer descriptors allocated per channel */
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#define MPC_DMA_DESCRIPTORS 64
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/* Macro definitions */
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#define MPC_DMA_CHANNELS 64
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#define MPC_DMA_TCD_OFFSET 0x1000
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/* Arbitration mode of group and channel */
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#define MPC_DMA_DMACR_EDCG (1 << 31)
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#define MPC_DMA_DMACR_ERGA (1 << 3)
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#define MPC_DMA_DMACR_ERCA (1 << 2)
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/* Error codes */
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#define MPC_DMA_DMAES_VLD (1 << 31)
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#define MPC_DMA_DMAES_GPE (1 << 15)
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#define MPC_DMA_DMAES_CPE (1 << 14)
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#define MPC_DMA_DMAES_ERRCHN(err) \
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(((err) >> 8) & 0x3f)
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#define MPC_DMA_DMAES_SAE (1 << 7)
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#define MPC_DMA_DMAES_SOE (1 << 6)
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#define MPC_DMA_DMAES_DAE (1 << 5)
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#define MPC_DMA_DMAES_DOE (1 << 4)
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#define MPC_DMA_DMAES_NCE (1 << 3)
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#define MPC_DMA_DMAES_SGE (1 << 2)
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#define MPC_DMA_DMAES_SBE (1 << 1)
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#define MPC_DMA_DMAES_DBE (1 << 0)
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#define MPC_DMA_DMAGPOR_SNOOP_ENABLE (1 << 6)
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#define MPC_DMA_TSIZE_1 0x00
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#define MPC_DMA_TSIZE_2 0x01
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#define MPC_DMA_TSIZE_4 0x02
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#define MPC_DMA_TSIZE_16 0x04
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#define MPC_DMA_TSIZE_32 0x05
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/* MPC5121 DMA engine registers */
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struct __attribute__ ((__packed__)) mpc_dma_regs {
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/* 0x00 */
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u32 dmacr; /* DMA control register */
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u32 dmaes; /* DMA error status */
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/* 0x08 */
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u32 dmaerqh; /* DMA enable request high(channels 63~32) */
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u32 dmaerql; /* DMA enable request low(channels 31~0) */
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u32 dmaeeih; /* DMA enable error interrupt high(ch63~32) */
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u32 dmaeeil; /* DMA enable error interrupt low(ch31~0) */
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/* 0x18 */
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u8 dmaserq; /* DMA set enable request */
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u8 dmacerq; /* DMA clear enable request */
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u8 dmaseei; /* DMA set enable error interrupt */
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u8 dmaceei; /* DMA clear enable error interrupt */
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/* 0x1c */
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u8 dmacint; /* DMA clear interrupt request */
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u8 dmacerr; /* DMA clear error */
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u8 dmassrt; /* DMA set start bit */
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u8 dmacdne; /* DMA clear DONE status bit */
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/* 0x20 */
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u32 dmainth; /* DMA interrupt request high(ch63~32) */
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u32 dmaintl; /* DMA interrupt request low(ch31~0) */
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u32 dmaerrh; /* DMA error high(ch63~32) */
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u32 dmaerrl; /* DMA error low(ch31~0) */
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/* 0x30 */
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u32 dmahrsh; /* DMA hw request status high(ch63~32) */
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u32 dmahrsl; /* DMA hardware request status low(ch31~0) */
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union {
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u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */
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u32 dmagpor; /* (General purpose register on MPC8308) */
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};
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u32 dmailsa; /* DMA interrupt low select AXE(ch31~0) */
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/* 0x40 ~ 0xff */
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u32 reserve0[48]; /* Reserved */
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/* 0x100 */
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u8 dchpri[MPC_DMA_CHANNELS];
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/* DMA channels(0~63) priority */
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};
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struct __attribute__ ((__packed__)) mpc_dma_tcd {
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/* 0x00 */
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u32 saddr; /* Source address */
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u32 smod:5; /* Source address modulo */
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u32 ssize:3; /* Source data transfer size */
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u32 dmod:5; /* Destination address modulo */
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u32 dsize:3; /* Destination data transfer size */
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u32 soff:16; /* Signed source address offset */
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/* 0x08 */
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u32 nbytes; /* Inner "minor" byte count */
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u32 slast; /* Last source address adjustment */
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u32 daddr; /* Destination address */
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/* 0x14 */
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u32 citer_elink:1; /* Enable channel-to-channel linking on
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* minor loop complete
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*/
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u32 citer_linkch:6; /* Link channel for minor loop complete */
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u32 citer:9; /* Current "major" iteration count */
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u32 doff:16; /* Signed destination address offset */
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/* 0x18 */
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u32 dlast_sga; /* Last Destination address adjustment/scatter
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* gather address
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*/
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/* 0x1c */
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u32 biter_elink:1; /* Enable channel-to-channel linking on major
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* loop complete
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*/
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u32 biter_linkch:6;
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u32 biter:9; /* Beginning "major" iteration count */
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u32 bwc:2; /* Bandwidth control */
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u32 major_linkch:6; /* Link channel number */
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u32 done:1; /* Channel done */
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u32 active:1; /* Channel active */
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u32 major_elink:1; /* Enable channel-to-channel linking on major
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* loop complete
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*/
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u32 e_sg:1; /* Enable scatter/gather processing */
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u32 d_req:1; /* Disable request */
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u32 int_half:1; /* Enable an interrupt when major counter is
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* half complete
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*/
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u32 int_maj:1; /* Enable an interrupt when major iteration
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* count completes
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*/
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u32 start:1; /* Channel start */
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};
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struct mpc_dma_desc {
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struct dma_async_tx_descriptor desc;
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struct mpc_dma_tcd *tcd;
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dma_addr_t tcd_paddr;
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int error;
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struct list_head node;
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};
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struct mpc_dma_chan {
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struct dma_chan chan;
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struct list_head free;
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struct list_head prepared;
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struct list_head queued;
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struct list_head active;
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struct list_head completed;
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struct mpc_dma_tcd *tcd;
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dma_addr_t tcd_paddr;
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/* Lock for this structure */
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spinlock_t lock;
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};
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struct mpc_dma {
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struct dma_device dma;
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struct tasklet_struct tasklet;
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struct mpc_dma_chan channels[MPC_DMA_CHANNELS];
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struct mpc_dma_regs __iomem *regs;
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struct mpc_dma_tcd __iomem *tcd;
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int irq;
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int irq2;
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uint error_status;
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int is_mpc8308;
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/* Lock for error_status field in this structure */
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spinlock_t error_status_lock;
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};
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#define DRV_NAME "mpc512x_dma"
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/* Convert struct dma_chan to struct mpc_dma_chan */
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static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c)
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{
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return container_of(c, struct mpc_dma_chan, chan);
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}
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/* Convert struct dma_chan to struct mpc_dma */
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static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c)
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{
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c);
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return container_of(mchan, struct mpc_dma, channels[c->chan_id]);
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}
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/*
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* Execute all queued DMA descriptors.
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*
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* Following requirements must be met while calling mpc_dma_execute():
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* a) mchan->lock is acquired,
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* b) mchan->active list is empty,
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* c) mchan->queued list contains at least one entry.
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*/
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static void mpc_dma_execute(struct mpc_dma_chan *mchan)
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{
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struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan);
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struct mpc_dma_desc *first = NULL;
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struct mpc_dma_desc *prev = NULL;
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struct mpc_dma_desc *mdesc;
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int cid = mchan->chan.chan_id;
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/* Move all queued descriptors to active list */
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list_splice_tail_init(&mchan->queued, &mchan->active);
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/* Chain descriptors into one transaction */
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list_for_each_entry(mdesc, &mchan->active, node) {
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if (!first)
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first = mdesc;
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if (!prev) {
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prev = mdesc;
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continue;
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}
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prev->tcd->dlast_sga = mdesc->tcd_paddr;
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prev->tcd->e_sg = 1;
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mdesc->tcd->start = 1;
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prev = mdesc;
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}
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prev->tcd->int_maj = 1;
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/* Send first descriptor in chain into hardware */
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memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd));
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if (first != prev)
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mdma->tcd[cid].e_sg = 1;
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out_8(&mdma->regs->dmassrt, cid);
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}
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/* Handle interrupt on one half of DMA controller (32 channels) */
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static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off)
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{
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struct mpc_dma_chan *mchan;
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struct mpc_dma_desc *mdesc;
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u32 status = is | es;
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int ch;
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while ((ch = fls(status) - 1) >= 0) {
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status &= ~(1 << ch);
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mchan = &mdma->channels[ch + off];
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spin_lock(&mchan->lock);
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out_8(&mdma->regs->dmacint, ch + off);
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out_8(&mdma->regs->dmacerr, ch + off);
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/* Check error status */
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if (es & (1 << ch))
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list_for_each_entry(mdesc, &mchan->active, node)
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mdesc->error = -EIO;
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/* Execute queued descriptors */
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list_splice_tail_init(&mchan->active, &mchan->completed);
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if (!list_empty(&mchan->queued))
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mpc_dma_execute(mchan);
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spin_unlock(&mchan->lock);
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}
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}
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/* Interrupt handler */
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static irqreturn_t mpc_dma_irq(int irq, void *data)
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{
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struct mpc_dma *mdma = data;
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uint es;
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/* Save error status register */
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es = in_be32(&mdma->regs->dmaes);
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spin_lock(&mdma->error_status_lock);
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if ((es & MPC_DMA_DMAES_VLD) && mdma->error_status == 0)
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mdma->error_status = es;
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spin_unlock(&mdma->error_status_lock);
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/* Handle interrupt on each channel */
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if (mdma->dma.chancnt > 32) {
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mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
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in_be32(&mdma->regs->dmaerrh), 32);
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}
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mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl),
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in_be32(&mdma->regs->dmaerrl), 0);
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/* Schedule tasklet */
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tasklet_schedule(&mdma->tasklet);
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return IRQ_HANDLED;
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}
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/* process completed descriptors */
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static void mpc_dma_process_completed(struct mpc_dma *mdma)
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{
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dma_cookie_t last_cookie = 0;
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struct mpc_dma_chan *mchan;
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struct mpc_dma_desc *mdesc;
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struct dma_async_tx_descriptor *desc;
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unsigned long flags;
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LIST_HEAD(list);
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int i;
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for (i = 0; i < mdma->dma.chancnt; i++) {
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mchan = &mdma->channels[i];
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/* Get all completed descriptors */
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spin_lock_irqsave(&mchan->lock, flags);
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if (!list_empty(&mchan->completed))
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list_splice_tail_init(&mchan->completed, &list);
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spin_unlock_irqrestore(&mchan->lock, flags);
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if (list_empty(&list))
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continue;
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/* Execute callbacks and run dependencies */
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list_for_each_entry(mdesc, &list, node) {
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desc = &mdesc->desc;
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if (desc->callback)
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desc->callback(desc->callback_param);
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last_cookie = desc->cookie;
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dma_run_dependencies(desc);
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}
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/* Free descriptors */
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spin_lock_irqsave(&mchan->lock, flags);
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list_splice_tail_init(&list, &mchan->free);
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mchan->chan.completed_cookie = last_cookie;
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spin_unlock_irqrestore(&mchan->lock, flags);
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}
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}
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/* DMA Tasklet */
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static void mpc_dma_tasklet(unsigned long data)
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{
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struct mpc_dma *mdma = (void *)data;
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unsigned long flags;
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uint es;
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spin_lock_irqsave(&mdma->error_status_lock, flags);
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es = mdma->error_status;
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mdma->error_status = 0;
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spin_unlock_irqrestore(&mdma->error_status_lock, flags);
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/* Print nice error report */
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if (es) {
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dev_err(mdma->dma.dev,
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"Hardware reported following error(s) on channel %u:\n",
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MPC_DMA_DMAES_ERRCHN(es));
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if (es & MPC_DMA_DMAES_GPE)
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dev_err(mdma->dma.dev, "- Group Priority Error\n");
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if (es & MPC_DMA_DMAES_CPE)
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dev_err(mdma->dma.dev, "- Channel Priority Error\n");
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if (es & MPC_DMA_DMAES_SAE)
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dev_err(mdma->dma.dev, "- Source Address Error\n");
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if (es & MPC_DMA_DMAES_SOE)
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dev_err(mdma->dma.dev, "- Source Offset"
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" Configuration Error\n");
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if (es & MPC_DMA_DMAES_DAE)
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dev_err(mdma->dma.dev, "- Destination Address"
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" Error\n");
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if (es & MPC_DMA_DMAES_DOE)
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dev_err(mdma->dma.dev, "- Destination Offset"
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" Configuration Error\n");
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if (es & MPC_DMA_DMAES_NCE)
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dev_err(mdma->dma.dev, "- NBytes/Citter"
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" Configuration Error\n");
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if (es & MPC_DMA_DMAES_SGE)
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dev_err(mdma->dma.dev, "- Scatter/Gather"
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" Configuration Error\n");
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if (es & MPC_DMA_DMAES_SBE)
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dev_err(mdma->dma.dev, "- Source Bus Error\n");
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if (es & MPC_DMA_DMAES_DBE)
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dev_err(mdma->dma.dev, "- Destination Bus Error\n");
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}
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mpc_dma_process_completed(mdma);
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}
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/* Submit descriptor to hardware */
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static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
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{
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(txd->chan);
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struct mpc_dma_desc *mdesc;
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unsigned long flags;
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dma_cookie_t cookie;
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mdesc = container_of(txd, struct mpc_dma_desc, desc);
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spin_lock_irqsave(&mchan->lock, flags);
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/* Move descriptor to queue */
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list_move_tail(&mdesc->node, &mchan->queued);
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/* If channel is idle, execute all queued descriptors */
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if (list_empty(&mchan->active))
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mpc_dma_execute(mchan);
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/* Update cookie */
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cookie = dma_cookie_assign(txd);
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spin_unlock_irqrestore(&mchan->lock, flags);
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return cookie;
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}
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/* Alloc channel resources */
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static int mpc_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
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struct mpc_dma_desc *mdesc;
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struct mpc_dma_tcd *tcd;
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dma_addr_t tcd_paddr;
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unsigned long flags;
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LIST_HEAD(descs);
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int i;
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/* Alloc DMA memory for Transfer Control Descriptors */
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tcd = dma_alloc_coherent(mdma->dma.dev,
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MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
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&tcd_paddr, GFP_KERNEL);
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if (!tcd)
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return -ENOMEM;
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/* Alloc descriptors for this channel */
|
|
for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) {
|
|
mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL);
|
|
if (!mdesc) {
|
|
dev_notice(mdma->dma.dev, "Memory allocation error. "
|
|
"Allocated only %u descriptors\n", i);
|
|
break;
|
|
}
|
|
|
|
dma_async_tx_descriptor_init(&mdesc->desc, chan);
|
|
mdesc->desc.flags = DMA_CTRL_ACK;
|
|
mdesc->desc.tx_submit = mpc_dma_tx_submit;
|
|
|
|
mdesc->tcd = &tcd[i];
|
|
mdesc->tcd_paddr = tcd_paddr + (i * sizeof(struct mpc_dma_tcd));
|
|
|
|
list_add_tail(&mdesc->node, &descs);
|
|
}
|
|
|
|
/* Return error only if no descriptors were allocated */
|
|
if (i == 0) {
|
|
dma_free_coherent(mdma->dma.dev,
|
|
MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
|
|
tcd, tcd_paddr);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
spin_lock_irqsave(&mchan->lock, flags);
|
|
mchan->tcd = tcd;
|
|
mchan->tcd_paddr = tcd_paddr;
|
|
list_splice_tail_init(&descs, &mchan->free);
|
|
spin_unlock_irqrestore(&mchan->lock, flags);
|
|
|
|
/* Enable Error Interrupt */
|
|
out_8(&mdma->regs->dmaseei, chan->chan_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Free channel resources */
|
|
static void mpc_dma_free_chan_resources(struct dma_chan *chan)
|
|
{
|
|
struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
|
|
struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
|
|
struct mpc_dma_desc *mdesc, *tmp;
|
|
struct mpc_dma_tcd *tcd;
|
|
dma_addr_t tcd_paddr;
|
|
unsigned long flags;
|
|
LIST_HEAD(descs);
|
|
|
|
spin_lock_irqsave(&mchan->lock, flags);
|
|
|
|
/* Channel must be idle */
|
|
BUG_ON(!list_empty(&mchan->prepared));
|
|
BUG_ON(!list_empty(&mchan->queued));
|
|
BUG_ON(!list_empty(&mchan->active));
|
|
BUG_ON(!list_empty(&mchan->completed));
|
|
|
|
/* Move data */
|
|
list_splice_tail_init(&mchan->free, &descs);
|
|
tcd = mchan->tcd;
|
|
tcd_paddr = mchan->tcd_paddr;
|
|
|
|
spin_unlock_irqrestore(&mchan->lock, flags);
|
|
|
|
/* Free DMA memory used by descriptors */
|
|
dma_free_coherent(mdma->dma.dev,
|
|
MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
|
|
tcd, tcd_paddr);
|
|
|
|
/* Free descriptors */
|
|
list_for_each_entry_safe(mdesc, tmp, &descs, node)
|
|
kfree(mdesc);
|
|
|
|
/* Disable Error Interrupt */
|
|
out_8(&mdma->regs->dmaceei, chan->chan_id);
|
|
}
|
|
|
|
/* Send all pending descriptor to hardware */
|
|
static void mpc_dma_issue_pending(struct dma_chan *chan)
|
|
{
|
|
/*
|
|
* We are posting descriptors to the hardware as soon as
|
|
* they are ready, so this function does nothing.
|
|
*/
|
|
}
|
|
|
|
/* Check request completion status */
|
|
static enum dma_status
|
|
mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
|
|
struct dma_tx_state *txstate)
|
|
{
|
|
struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
|
|
unsigned long flags;
|
|
dma_cookie_t last_used;
|
|
dma_cookie_t last_complete;
|
|
|
|
spin_lock_irqsave(&mchan->lock, flags);
|
|
last_used = mchan->chan.cookie;
|
|
last_complete = mchan->chan.completed_cookie;
|
|
spin_unlock_irqrestore(&mchan->lock, flags);
|
|
|
|
dma_set_tx_state(txstate, last_complete, last_used, 0);
|
|
return dma_async_is_complete(cookie, last_complete, last_used);
|
|
}
|
|
|
|
/* Prepare descriptor for memory to memory copy */
|
|
static struct dma_async_tx_descriptor *
|
|
mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
|
|
size_t len, unsigned long flags)
|
|
{
|
|
struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
|
|
struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
|
|
struct mpc_dma_desc *mdesc = NULL;
|
|
struct mpc_dma_tcd *tcd;
|
|
unsigned long iflags;
|
|
|
|
/* Get free descriptor */
|
|
spin_lock_irqsave(&mchan->lock, iflags);
|
|
if (!list_empty(&mchan->free)) {
|
|
mdesc = list_first_entry(&mchan->free, struct mpc_dma_desc,
|
|
node);
|
|
list_del(&mdesc->node);
|
|
}
|
|
spin_unlock_irqrestore(&mchan->lock, iflags);
|
|
|
|
if (!mdesc) {
|
|
/* try to free completed descriptors */
|
|
mpc_dma_process_completed(mdma);
|
|
return NULL;
|
|
}
|
|
|
|
mdesc->error = 0;
|
|
tcd = mdesc->tcd;
|
|
|
|
/* Prepare Transfer Control Descriptor for this transaction */
|
|
memset(tcd, 0, sizeof(struct mpc_dma_tcd));
|
|
|
|
if (IS_ALIGNED(src | dst | len, 32)) {
|
|
tcd->ssize = MPC_DMA_TSIZE_32;
|
|
tcd->dsize = MPC_DMA_TSIZE_32;
|
|
tcd->soff = 32;
|
|
tcd->doff = 32;
|
|
} else if (!mdma->is_mpc8308 && IS_ALIGNED(src | dst | len, 16)) {
|
|
/* MPC8308 doesn't support 16 byte transfers */
|
|
tcd->ssize = MPC_DMA_TSIZE_16;
|
|
tcd->dsize = MPC_DMA_TSIZE_16;
|
|
tcd->soff = 16;
|
|
tcd->doff = 16;
|
|
} else if (IS_ALIGNED(src | dst | len, 4)) {
|
|
tcd->ssize = MPC_DMA_TSIZE_4;
|
|
tcd->dsize = MPC_DMA_TSIZE_4;
|
|
tcd->soff = 4;
|
|
tcd->doff = 4;
|
|
} else if (IS_ALIGNED(src | dst | len, 2)) {
|
|
tcd->ssize = MPC_DMA_TSIZE_2;
|
|
tcd->dsize = MPC_DMA_TSIZE_2;
|
|
tcd->soff = 2;
|
|
tcd->doff = 2;
|
|
} else {
|
|
tcd->ssize = MPC_DMA_TSIZE_1;
|
|
tcd->dsize = MPC_DMA_TSIZE_1;
|
|
tcd->soff = 1;
|
|
tcd->doff = 1;
|
|
}
|
|
|
|
tcd->saddr = src;
|
|
tcd->daddr = dst;
|
|
tcd->nbytes = len;
|
|
tcd->biter = 1;
|
|
tcd->citer = 1;
|
|
|
|
/* Place descriptor in prepared list */
|
|
spin_lock_irqsave(&mchan->lock, iflags);
|
|
list_add_tail(&mdesc->node, &mchan->prepared);
|
|
spin_unlock_irqrestore(&mchan->lock, iflags);
|
|
|
|
return &mdesc->desc;
|
|
}
|
|
|
|
static int __devinit mpc_dma_probe(struct platform_device *op)
|
|
{
|
|
struct device_node *dn = op->dev.of_node;
|
|
struct device *dev = &op->dev;
|
|
struct dma_device *dma;
|
|
struct mpc_dma *mdma;
|
|
struct mpc_dma_chan *mchan;
|
|
struct resource res;
|
|
ulong regs_start, regs_size;
|
|
int retval, i;
|
|
|
|
mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL);
|
|
if (!mdma) {
|
|
dev_err(dev, "Memory exhausted!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mdma->irq = irq_of_parse_and_map(dn, 0);
|
|
if (mdma->irq == NO_IRQ) {
|
|
dev_err(dev, "Error mapping IRQ!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (of_device_is_compatible(dn, "fsl,mpc8308-dma")) {
|
|
mdma->is_mpc8308 = 1;
|
|
mdma->irq2 = irq_of_parse_and_map(dn, 1);
|
|
if (mdma->irq2 == NO_IRQ) {
|
|
dev_err(dev, "Error mapping IRQ!\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
retval = of_address_to_resource(dn, 0, &res);
|
|
if (retval) {
|
|
dev_err(dev, "Error parsing memory region!\n");
|
|
return retval;
|
|
}
|
|
|
|
regs_start = res.start;
|
|
regs_size = resource_size(&res);
|
|
|
|
if (!devm_request_mem_region(dev, regs_start, regs_size, DRV_NAME)) {
|
|
dev_err(dev, "Error requesting memory region!\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
mdma->regs = devm_ioremap(dev, regs_start, regs_size);
|
|
if (!mdma->regs) {
|
|
dev_err(dev, "Error mapping memory region!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mdma->tcd = (struct mpc_dma_tcd *)((u8 *)(mdma->regs)
|
|
+ MPC_DMA_TCD_OFFSET);
|
|
|
|
retval = devm_request_irq(dev, mdma->irq, &mpc_dma_irq, 0, DRV_NAME,
|
|
mdma);
|
|
if (retval) {
|
|
dev_err(dev, "Error requesting IRQ!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (mdma->is_mpc8308) {
|
|
retval = devm_request_irq(dev, mdma->irq2, &mpc_dma_irq, 0,
|
|
DRV_NAME, mdma);
|
|
if (retval) {
|
|
dev_err(dev, "Error requesting IRQ2!\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
spin_lock_init(&mdma->error_status_lock);
|
|
|
|
dma = &mdma->dma;
|
|
dma->dev = dev;
|
|
if (!mdma->is_mpc8308)
|
|
dma->chancnt = MPC_DMA_CHANNELS;
|
|
else
|
|
dma->chancnt = 16; /* MPC8308 DMA has only 16 channels */
|
|
dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources;
|
|
dma->device_free_chan_resources = mpc_dma_free_chan_resources;
|
|
dma->device_issue_pending = mpc_dma_issue_pending;
|
|
dma->device_tx_status = mpc_dma_tx_status;
|
|
dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy;
|
|
|
|
INIT_LIST_HEAD(&dma->channels);
|
|
dma_cap_set(DMA_MEMCPY, dma->cap_mask);
|
|
|
|
for (i = 0; i < dma->chancnt; i++) {
|
|
mchan = &mdma->channels[i];
|
|
|
|
mchan->chan.device = dma;
|
|
mchan->chan.cookie = 1;
|
|
mchan->chan.completed_cookie = mchan->chan.cookie;
|
|
|
|
INIT_LIST_HEAD(&mchan->free);
|
|
INIT_LIST_HEAD(&mchan->prepared);
|
|
INIT_LIST_HEAD(&mchan->queued);
|
|
INIT_LIST_HEAD(&mchan->active);
|
|
INIT_LIST_HEAD(&mchan->completed);
|
|
|
|
spin_lock_init(&mchan->lock);
|
|
list_add_tail(&mchan->chan.device_node, &dma->channels);
|
|
}
|
|
|
|
tasklet_init(&mdma->tasklet, mpc_dma_tasklet, (unsigned long)mdma);
|
|
|
|
/*
|
|
* Configure DMA Engine:
|
|
* - Dynamic clock,
|
|
* - Round-robin group arbitration,
|
|
* - Round-robin channel arbitration.
|
|
*/
|
|
if (!mdma->is_mpc8308) {
|
|
out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
|
|
MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA);
|
|
|
|
/* Disable hardware DMA requests */
|
|
out_be32(&mdma->regs->dmaerqh, 0);
|
|
out_be32(&mdma->regs->dmaerql, 0);
|
|
|
|
/* Disable error interrupts */
|
|
out_be32(&mdma->regs->dmaeeih, 0);
|
|
out_be32(&mdma->regs->dmaeeil, 0);
|
|
|
|
/* Clear interrupts status */
|
|
out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
|
|
out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
|
|
out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
|
|
out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
|
|
|
|
/* Route interrupts to IPIC */
|
|
out_be32(&mdma->regs->dmaihsa, 0);
|
|
out_be32(&mdma->regs->dmailsa, 0);
|
|
} else {
|
|
/* MPC8308 has 16 channels and lacks some registers */
|
|
out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA);
|
|
|
|
/* enable snooping */
|
|
out_be32(&mdma->regs->dmagpor, MPC_DMA_DMAGPOR_SNOOP_ENABLE);
|
|
/* Disable error interrupts */
|
|
out_be32(&mdma->regs->dmaeeil, 0);
|
|
|
|
/* Clear interrupts status */
|
|
out_be32(&mdma->regs->dmaintl, 0xFFFF);
|
|
out_be32(&mdma->regs->dmaerrl, 0xFFFF);
|
|
}
|
|
|
|
/* Register DMA engine */
|
|
dev_set_drvdata(dev, mdma);
|
|
retval = dma_async_device_register(dma);
|
|
if (retval) {
|
|
devm_free_irq(dev, mdma->irq, mdma);
|
|
irq_dispose_mapping(mdma->irq);
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int __devexit mpc_dma_remove(struct platform_device *op)
|
|
{
|
|
struct device *dev = &op->dev;
|
|
struct mpc_dma *mdma = dev_get_drvdata(dev);
|
|
|
|
dma_async_device_unregister(&mdma->dma);
|
|
devm_free_irq(dev, mdma->irq, mdma);
|
|
irq_dispose_mapping(mdma->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id mpc_dma_match[] = {
|
|
{ .compatible = "fsl,mpc5121-dma", },
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver mpc_dma_driver = {
|
|
.probe = mpc_dma_probe,
|
|
.remove = __devexit_p(mpc_dma_remove),
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = mpc_dma_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mpc_dma_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>");
|