3d5ae6b69e
We create a local header file entry.h, under arch/sparc64/kernel/, that we can use to declare routines either defined in assembler or only invoked from assembler. As well as other data objects which are private to the inner sparc64 kernel arch code. Signed-off-by: David S. Miller <davem@davemloft.net>
157 lines
3.9 KiB
C
157 lines
3.9 KiB
C
/* cpu.c: Dinky routines to look for the kind of Sparc cpu
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* we are on.
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*
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* Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/asi.h>
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#include <asm/system.h>
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#include <asm/fpumacro.h>
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#include <asm/cpudata.h>
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#include <asm/spitfire.h>
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#include <asm/oplib.h>
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#include "entry.h"
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DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
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struct cpu_iu_info {
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short manuf;
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short impl;
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char* cpu_name; /* should be enough I hope... */
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};
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struct cpu_fp_info {
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short manuf;
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short impl;
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char fpu_vers;
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char* fp_name;
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};
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static struct cpu_fp_info linux_sparc_fpu[] = {
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{ 0x17, 0x10, 0, "UltraSparc I integrated FPU"},
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{ 0x22, 0x10, 0, "UltraSparc I integrated FPU"},
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{ 0x17, 0x11, 0, "UltraSparc II integrated FPU"},
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{ 0x17, 0x12, 0, "UltraSparc IIi integrated FPU"},
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{ 0x17, 0x13, 0, "UltraSparc IIe integrated FPU"},
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{ 0x3e, 0x14, 0, "UltraSparc III integrated FPU"},
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{ 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
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{ 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
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{ 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
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{ 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},
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{ 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},
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};
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#define NSPARCFPU ARRAY_SIZE(linux_sparc_fpu)
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static struct cpu_iu_info linux_sparc_chips[] = {
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{ 0x17, 0x10, "TI UltraSparc I (SpitFire)"},
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{ 0x22, 0x10, "TI UltraSparc I (SpitFire)"},
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{ 0x17, 0x11, "TI UltraSparc II (BlackBird)"},
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{ 0x17, 0x12, "TI UltraSparc IIi (Sabre)"},
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{ 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)"},
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{ 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
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{ 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
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{ 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
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{ 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
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{ 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
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{ 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
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};
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#define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips)
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char *sparc_cpu_type;
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char *sparc_fpu_type;
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static void __init sun4v_cpu_probe(void)
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{
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_NIAGARA1:
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sparc_cpu_type = "UltraSparc T1 (Niagara)";
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sparc_fpu_type = "UltraSparc T1 integrated FPU";
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break;
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case SUN4V_CHIP_NIAGARA2:
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sparc_cpu_type = "UltraSparc T2 (Niagara2)";
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sparc_fpu_type = "UltraSparc T2 integrated FPU";
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break;
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default:
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printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
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prom_cpu_compatible);
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sparc_cpu_type = "Unknown SUN4V CPU";
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sparc_fpu_type = "Unknown SUN4V FPU";
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break;
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}
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}
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void __init cpu_probe(void)
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{
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unsigned long ver, fpu_vers, manuf, impl, fprs;
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int i;
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if (tlb_type == hypervisor) {
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sun4v_cpu_probe();
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return;
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}
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fprs = fprs_read();
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fprs_write(FPRS_FEF);
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__asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
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: "=&r" (ver)
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: "r" (&fpu_vers));
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fprs_write(fprs);
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manuf = ((ver >> 48) & 0xffff);
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impl = ((ver >> 32) & 0xffff);
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fpu_vers = ((fpu_vers >> 17) & 0x7);
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retry:
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for (i = 0; i < NSPARCCHIPS; i++) {
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if (linux_sparc_chips[i].manuf == manuf) {
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if (linux_sparc_chips[i].impl == impl) {
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sparc_cpu_type =
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linux_sparc_chips[i].cpu_name;
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break;
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}
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}
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}
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if (i == NSPARCCHIPS) {
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/* Maybe it is a cheetah+ derivative, report it as cheetah+
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* in that case until we learn the real names.
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*/
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if (manuf == 0x3e &&
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impl > 0x15) {
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impl = 0x15;
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goto retry;
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} else {
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printk("DEBUG: manuf[%lx] impl[%lx]\n",
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manuf, impl);
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}
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sparc_cpu_type = "Unknown CPU";
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}
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for (i = 0; i < NSPARCFPU; i++) {
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if (linux_sparc_fpu[i].manuf == manuf &&
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linux_sparc_fpu[i].impl == impl) {
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if (linux_sparc_fpu[i].fpu_vers == fpu_vers) {
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sparc_fpu_type =
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linux_sparc_fpu[i].fp_name;
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break;
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}
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}
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}
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if (i == NSPARCFPU) {
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printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
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manuf, impl, fpu_vers);
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sparc_fpu_type = "Unknown FPU";
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}
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}
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