1727339590
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
129 lines
3.6 KiB
C
129 lines
3.6 KiB
C
/**
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* timer-ti-32k.c - OMAP2 32k Timer Support
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*
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* Copyright (C) 2009 Nokia Corporation
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*
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* Update to use new clocksource/clockevent layers
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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*
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* Original driver:
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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* Juha Yrjölä <juha.yrjola@nokia.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* Some parts based off of TI's 24xx code:
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*
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* Copyright (C) 2004-2009 Texas Instruments, Inc.
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*
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* Roughly modelled after the OMAP1 MPU timer code.
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/sched_clock.h>
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#include <linux/clocksource.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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#define OMAP2_32KSYNCNT_REV_OFF 0x0
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#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
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#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
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#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
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struct ti_32k {
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void __iomem *base;
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void __iomem *counter;
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struct clocksource cs;
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};
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static inline struct ti_32k *to_ti_32k(struct clocksource *cs)
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{
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return container_of(cs, struct ti_32k, cs);
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}
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static u64 notrace ti_32k_read_cycles(struct clocksource *cs)
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{
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struct ti_32k *ti = to_ti_32k(cs);
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return (u64)readl_relaxed(ti->counter);
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}
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static struct ti_32k ti_32k_timer = {
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.cs = {
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.name = "32k_counter",
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.rating = 250,
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.read = ti_32k_read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS |
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CLOCK_SOURCE_SUSPEND_NONSTOP,
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},
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};
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static u64 notrace omap_32k_read_sched_clock(void)
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{
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return ti_32k_read_cycles(&ti_32k_timer.cs);
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}
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static int __init ti_32k_timer_init(struct device_node *np)
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{
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int ret;
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ti_32k_timer.base = of_iomap(np, 0);
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if (!ti_32k_timer.base) {
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pr_err("Can't ioremap 32k timer base\n");
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return -ENXIO;
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}
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ti_32k_timer.counter = ti_32k_timer.base;
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/*
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* 32k sync Counter IP register offsets vary between the highlander
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* version and the legacy ones.
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*
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* The 'SCHEME' bits(30-31) of the revision register is used to identify
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* the version.
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*/
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if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) &
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OMAP2_32KSYNCNT_REV_SCHEME)
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ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH;
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else
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ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
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ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
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if (ret) {
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pr_err("32k_counter: can't register clocksource\n");
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return ret;
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}
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sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
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pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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return 0;
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}
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TIMER_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k",
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ti_32k_timer_init);
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