99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#ifndef __RTL8723A_PG_H__
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#define __RTL8723A_PG_H__
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/* EEPROM/Efuse PG Offset for 8723E/8723U/8723S */
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#define EEPROM_CCK_TX_PWR_INX_8723A 0x10
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#define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16
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#define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C
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#define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F
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#define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22
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#define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25
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#define EEPROM_ChannelPlan_8723A 0x28
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#define EEPROM_TSSI_A_8723A 0x29
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#define EEPROM_THERMAL_METER_8723A 0x2A
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#define RF_OPTION1_8723A 0x2B
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#define RF_OPTION2_8723A 0x2C
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#define RF_OPTION3_8723A 0x2D
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#define RF_OPTION4_8723A 0x2E
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#define EEPROM_VERSION_8723A 0x30
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#define EEPROM_CustomID_8723A 0x31
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#define EEPROM_SubCustomID_8723A 0x32
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#define EEPROM_XTAL_K_8723A 0x33
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#define EEPROM_Chipset_8723A 0x34
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/* RTL8723AE */
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#define EEPROM_VID_8723AE 0x49
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#define EEPROM_DID_8723AE 0x4B
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#define EEPROM_SVID_8723AE 0x4D
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#define EEPROM_SMID_8723AE 0x4F
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#define EEPROM_MAC_ADDR_8723AE 0x67
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/* RTL8723AU */
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#define EEPROM_MAC_ADDR_8723AU 0xC6
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#define EEPROM_VID_8723AU 0xB7
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#define EEPROM_PID_8723AU 0xB9
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/* RTL8723AS */
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#define EEPROM_MAC_ADDR_8723AS 0xAA
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/* EEPROM/Efuse Value Type */
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#define EETYPE_TX_PWR 0x0
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/* EEPROM/Efuse Default Value */
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#define EEPROM_Default_CrystalCap_8723A 0x20
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/* EEPROM/EFUSE data structure definition. */
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#define MAX_CHNL_GROUP 3+9
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struct txpowerinfo {
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u8 CCKIndex[RF_PATH_MAX][MAX_CHNL_GROUP];
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u8 HT40_1SIndex[RF_PATH_MAX][MAX_CHNL_GROUP];
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u8 HT40_2SIndexDiff[RF_PATH_MAX][MAX_CHNL_GROUP];
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u8 HT20IndexDiff[RF_PATH_MAX][MAX_CHNL_GROUP];
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u8 OFDMIndexDiff[RF_PATH_MAX][MAX_CHNL_GROUP];
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u8 HT40MaxOffset[RF_PATH_MAX][MAX_CHNL_GROUP];
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u8 HT20MaxOffset[RF_PATH_MAX][MAX_CHNL_GROUP];
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u8 TSSI_A[3];
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u8 TSSI_B[3];
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u8 TSSI_A_5G[3]; /* 5GL/5GM/5GH */
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u8 TSSI_B_5G[3];
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};
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enum bt_ant_num {
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Ant_x2 = 0,
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Ant_x1 = 1
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};
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enum bt_cotype {
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BT_2Wire = 0,
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BT_ISSC_3Wire = 1,
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BT_Accel = 2,
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BT_CSR_BC4 = 3,
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BT_CSR_BC8 = 4,
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BT_RTL8756 = 5,
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BT_RTL8723A = 6
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};
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enum bt_radioshared {
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BT_Radio_Shared = 0,
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BT_Radio_Individual = 1,
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};
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#endif
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