![Philipp Zabel](/assets/img/avatar_default.png)
Commit a53e35db70
("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.
No functional changes.
Cc: Marc Dietrich <marvin24@gmx.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-tegra@vger.kernel.org
Cc: devel@driverdev.osuosl.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
989 lines
26 KiB
C
989 lines
26 KiB
C
/*
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* NVEC: NVIDIA compliant embedded controller interface
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*
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* Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net>
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*
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* Authors: Pierre-Hugues Husson <phhusson@free.fr>
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* Ilya Petrov <ilya.muromec@gmail.com>
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* Marc Dietrich <marvin24@gmx.de>
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* Julian Andres Klode <jak@jak-linux.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/atomic.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/list.h>
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#include <linux/mfd/core.h>
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#include <linux/mutex.h>
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#include <linux/notifier.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include "nvec.h"
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#define I2C_CNFG 0x00
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#define I2C_CNFG_PACKET_MODE_EN BIT(10)
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#define I2C_CNFG_NEW_MASTER_SFM BIT(11)
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#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
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#define I2C_SL_CNFG 0x20
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#define I2C_SL_NEWSL BIT(2)
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#define I2C_SL_NACK BIT(1)
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#define I2C_SL_RESP BIT(0)
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#define I2C_SL_IRQ BIT(3)
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#define END_TRANS BIT(4)
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#define RCVD BIT(2)
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#define RNW BIT(1)
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#define I2C_SL_RCVD 0x24
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#define I2C_SL_STATUS 0x28
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#define I2C_SL_ADDR1 0x2c
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#define I2C_SL_ADDR2 0x30
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#define I2C_SL_DELAY_COUNT 0x3c
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/**
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* enum nvec_msg_category - Message categories for nvec_msg_alloc()
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* @NVEC_MSG_RX: The message is an incoming message (from EC)
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* @NVEC_MSG_TX: The message is an outgoing message (to EC)
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*/
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enum nvec_msg_category {
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NVEC_MSG_RX,
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NVEC_MSG_TX,
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};
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enum nvec_sleep_subcmds {
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GLOBAL_EVENTS,
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AP_PWR_DOWN,
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AP_SUSPEND,
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};
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#define CNF_EVENT_REPORTING 0x01
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#define GET_FIRMWARE_VERSION 0x15
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#define LID_SWITCH BIT(1)
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#define PWR_BUTTON BIT(15)
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static struct nvec_chip *nvec_power_handle;
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static const struct mfd_cell nvec_devices[] = {
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{
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.name = "nvec-kbd",
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},
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{
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.name = "nvec-mouse",
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},
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{
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.name = "nvec-power",
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.id = 0,
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},
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{
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.name = "nvec-power",
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.id = 1,
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},
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{
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.name = "nvec-paz00",
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},
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};
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/**
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* nvec_register_notifier - Register a notifier with nvec
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* @nvec: A &struct nvec_chip
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* @nb: The notifier block to register
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*
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* Registers a notifier with @nvec. The notifier will be added to an atomic
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* notifier chain that is called for all received messages except those that
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* correspond to a request initiated by nvec_write_sync().
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*/
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int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb,
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unsigned int events)
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{
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return atomic_notifier_chain_register(&nvec->notifier_list, nb);
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}
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EXPORT_SYMBOL_GPL(nvec_register_notifier);
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/**
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* nvec_unregister_notifier - Unregister a notifier with nvec
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* @nvec: A &struct nvec_chip
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* @nb: The notifier block to unregister
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*
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* Unregisters a notifier with @nvec. The notifier will be removed from the
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* atomic notifier chain.
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*/
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int nvec_unregister_notifier(struct nvec_chip *nvec, struct notifier_block *nb)
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{
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return atomic_notifier_chain_unregister(&nvec->notifier_list, nb);
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}
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EXPORT_SYMBOL_GPL(nvec_unregister_notifier);
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/**
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* nvec_status_notifier - The final notifier
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*
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* Prints a message about control events not handled in the notifier
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* chain.
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*/
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static int nvec_status_notifier(struct notifier_block *nb,
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unsigned long event_type, void *data)
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{
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struct nvec_chip *nvec = container_of(nb, struct nvec_chip,
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nvec_status_notifier);
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unsigned char *msg = data;
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if (event_type != NVEC_CNTL)
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return NOTIFY_DONE;
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dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type);
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print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1,
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msg, msg[1] + 2, true);
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return NOTIFY_OK;
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}
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/**
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* nvec_msg_alloc:
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* @nvec: A &struct nvec_chip
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* @category: Pool category, see &enum nvec_msg_category
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*
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* Allocate a single &struct nvec_msg object from the message pool of
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* @nvec. The result shall be passed to nvec_msg_free() if no longer
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* used.
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*
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* Outgoing messages are placed in the upper 75% of the pool, keeping the
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* lower 25% available for RX buffers only. The reason is to prevent a
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* situation where all buffers are full and a message is thus endlessly
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* retried because the response could never be processed.
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*/
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static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec,
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enum nvec_msg_category category)
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{
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int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0;
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for (; i < NVEC_POOL_SIZE; i++) {
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if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) {
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dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i);
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return &nvec->msg_pool[i];
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}
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}
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dev_err(nvec->dev, "could not allocate %s buffer\n",
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(category == NVEC_MSG_TX) ? "TX" : "RX");
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return NULL;
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}
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/**
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* nvec_msg_free:
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* @nvec: A &struct nvec_chip
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* @msg: A message (must be allocated by nvec_msg_alloc() and belong to @nvec)
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*
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* Free the given message
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*/
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void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg)
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{
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if (msg != &nvec->tx_scratch)
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dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool);
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atomic_set(&msg->used, 0);
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}
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EXPORT_SYMBOL_GPL(nvec_msg_free);
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/**
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* nvec_msg_is_event - Return %true if @msg is an event
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* @msg: A message
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*/
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static bool nvec_msg_is_event(struct nvec_msg *msg)
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{
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return msg->data[0] >> 7;
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}
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/**
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* nvec_msg_size - Get the size of a message
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* @msg: The message to get the size for
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*
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* This only works for received messages, not for outgoing messages.
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*/
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static size_t nvec_msg_size(struct nvec_msg *msg)
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{
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bool is_event = nvec_msg_is_event(msg);
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int event_length = (msg->data[0] & 0x60) >> 5;
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/* for variable size, payload size in byte 1 + count (1) + cmd (1) */
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if (!is_event || event_length == NVEC_VAR_SIZE)
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return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0;
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else if (event_length == NVEC_2BYTES)
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return 2;
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else if (event_length == NVEC_3BYTES)
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return 3;
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return 0;
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}
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/**
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* nvec_gpio_set_value - Set the GPIO value
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* @nvec: A &struct nvec_chip
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* @value: The value to write (0 or 1)
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*
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* Like gpio_set_value(), but generating debugging information
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*/
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static void nvec_gpio_set_value(struct nvec_chip *nvec, int value)
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{
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dev_dbg(nvec->dev, "GPIO changed from %u to %u\n",
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gpio_get_value(nvec->gpio), value);
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gpio_set_value(nvec->gpio, value);
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}
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/**
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* nvec_write_async - Asynchronously write a message to NVEC
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* @nvec: An nvec_chip instance
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* @data: The message data, starting with the request type
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* @size: The size of @data
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*
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* Queue a single message to be transferred to the embedded controller
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* and return immediately.
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*
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* Returns: 0 on success, a negative error code on failure. If a failure
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* occurred, the nvec driver may print an error.
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*/
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int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data,
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short size)
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{
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struct nvec_msg *msg;
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unsigned long flags;
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msg = nvec_msg_alloc(nvec, NVEC_MSG_TX);
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if (!msg)
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return -ENOMEM;
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msg->data[0] = size;
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memcpy(msg->data + 1, data, size);
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msg->size = size + 1;
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spin_lock_irqsave(&nvec->tx_lock, flags);
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list_add_tail(&msg->node, &nvec->tx_data);
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spin_unlock_irqrestore(&nvec->tx_lock, flags);
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schedule_work(&nvec->tx_work);
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return 0;
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}
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EXPORT_SYMBOL(nvec_write_async);
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/**
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* nvec_write_sync - Write a message to nvec and read the response
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* @nvec: An &struct nvec_chip
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* @data: The data to write
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* @size: The size of @data
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* @msg: The response message received
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*
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* This is similar to nvec_write_async(), but waits for the
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* request to be answered before returning. This function
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* uses a mutex and can thus not be called from e.g.
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* interrupt handlers.
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*
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* Returns: 0 on success, a negative error code on failure.
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* The response message is returned in @msg. Shall be freed with
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* with nvec_msg_free() once no longer used.
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*
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*/
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int nvec_write_sync(struct nvec_chip *nvec,
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const unsigned char *data, short size,
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struct nvec_msg **msg)
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{
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mutex_lock(&nvec->sync_write_mutex);
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*msg = NULL;
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nvec->sync_write_pending = (data[1] << 8) + data[0];
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if (nvec_write_async(nvec, data, size) < 0) {
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mutex_unlock(&nvec->sync_write_mutex);
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return -ENOMEM;
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}
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dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n",
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nvec->sync_write_pending);
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if (!(wait_for_completion_timeout(&nvec->sync_write,
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msecs_to_jiffies(2000)))) {
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dev_warn(nvec->dev,
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"timeout waiting for sync write to complete\n");
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mutex_unlock(&nvec->sync_write_mutex);
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return -ETIMEDOUT;
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}
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dev_dbg(nvec->dev, "nvec_sync_write: pong!\n");
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*msg = nvec->last_sync_msg;
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mutex_unlock(&nvec->sync_write_mutex);
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return 0;
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}
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EXPORT_SYMBOL(nvec_write_sync);
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/**
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* nvec_toggle_global_events - enables or disables global event reporting
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* @nvec: nvec handle
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* @state: true for enable, false for disable
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*
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* This switches on/off global event reports by the embedded controller.
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*/
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static void nvec_toggle_global_events(struct nvec_chip *nvec, bool state)
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{
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unsigned char global_events[] = { NVEC_SLEEP, GLOBAL_EVENTS, state };
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nvec_write_async(nvec, global_events, 3);
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}
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/**
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* nvec_event_mask - fill the command string with event bitfield
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* ev: points to event command string
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* mask: bit to insert into the event mask
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*
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* Configure event command expects a 32 bit bitfield which describes
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* which events to enable. The bitfield has the following structure
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* (from highest byte to lowest):
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* system state bits 7-0
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* system state bits 15-8
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* oem system state bits 7-0
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* oem system state bits 15-8
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*/
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static void nvec_event_mask(char *ev, u32 mask)
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{
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ev[3] = mask >> 16 & 0xff;
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ev[4] = mask >> 24 & 0xff;
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ev[5] = mask >> 0 & 0xff;
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ev[6] = mask >> 8 & 0xff;
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}
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/**
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* nvec_request_master - Process outgoing messages
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* @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
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*
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* Processes all outgoing requests by sending the request and awaiting the
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* response, then continuing with the next request. Once a request has a
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* matching response, it will be freed and removed from the list.
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*/
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static void nvec_request_master(struct work_struct *work)
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{
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struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work);
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unsigned long flags;
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long err;
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struct nvec_msg *msg;
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spin_lock_irqsave(&nvec->tx_lock, flags);
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while (!list_empty(&nvec->tx_data)) {
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msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node);
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spin_unlock_irqrestore(&nvec->tx_lock, flags);
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nvec_gpio_set_value(nvec, 0);
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err = wait_for_completion_interruptible_timeout(
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&nvec->ec_transfer, msecs_to_jiffies(5000));
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if (err == 0) {
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dev_warn(nvec->dev, "timeout waiting for ec transfer\n");
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nvec_gpio_set_value(nvec, 1);
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msg->pos = 0;
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}
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spin_lock_irqsave(&nvec->tx_lock, flags);
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if (err > 0) {
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list_del_init(&msg->node);
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nvec_msg_free(nvec, msg);
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}
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}
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spin_unlock_irqrestore(&nvec->tx_lock, flags);
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}
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/**
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* parse_msg - Print some information and call the notifiers on an RX message
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* @nvec: A &struct nvec_chip
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* @msg: A message received by @nvec
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*
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* Paarse some pieces of the message and then call the chain of notifiers
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* registered via nvec_register_notifier.
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*/
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static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg)
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{
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if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) {
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dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data);
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return -EINVAL;
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}
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if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5)
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print_hex_dump(KERN_WARNING, "ec system event ",
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DUMP_PREFIX_NONE, 16, 1, msg->data,
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msg->data[1] + 2, true);
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atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f,
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msg->data);
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return 0;
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}
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/**
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* nvec_dispatch - Process messages received from the EC
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* @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
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*
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* Process messages previously received from the EC and put into the RX
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* queue of the &struct nvec_chip instance associated with @work.
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*/
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static void nvec_dispatch(struct work_struct *work)
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{
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struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work);
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unsigned long flags;
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struct nvec_msg *msg;
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spin_lock_irqsave(&nvec->rx_lock, flags);
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while (!list_empty(&nvec->rx_data)) {
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msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node);
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list_del_init(&msg->node);
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spin_unlock_irqrestore(&nvec->rx_lock, flags);
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if (nvec->sync_write_pending ==
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(msg->data[2] << 8) + msg->data[0]) {
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dev_dbg(nvec->dev, "sync write completed!\n");
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nvec->sync_write_pending = 0;
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nvec->last_sync_msg = msg;
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complete(&nvec->sync_write);
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} else {
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parse_msg(nvec, msg);
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nvec_msg_free(nvec, msg);
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}
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spin_lock_irqsave(&nvec->rx_lock, flags);
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}
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spin_unlock_irqrestore(&nvec->rx_lock, flags);
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}
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/**
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* nvec_tx_completed - Complete the current transfer
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* @nvec: A &struct nvec_chip
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*
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* This is called when we have received an END_TRANS on a TX transfer.
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*/
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static void nvec_tx_completed(struct nvec_chip *nvec)
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{
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/* We got an END_TRANS, let's skip this, maybe there's an event */
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if (nvec->tx->pos != nvec->tx->size) {
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dev_err(nvec->dev, "premature END_TRANS, resending\n");
|
|
nvec->tx->pos = 0;
|
|
nvec_gpio_set_value(nvec, 0);
|
|
} else {
|
|
nvec->state = 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* nvec_rx_completed - Complete the current transfer
|
|
* @nvec: A &struct nvec_chip
|
|
*
|
|
* This is called when we have received an END_TRANS on a RX transfer.
|
|
*/
|
|
static void nvec_rx_completed(struct nvec_chip *nvec)
|
|
{
|
|
if (nvec->rx->pos != nvec_msg_size(nvec->rx)) {
|
|
dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n",
|
|
(uint)nvec_msg_size(nvec->rx),
|
|
(uint)nvec->rx->pos);
|
|
|
|
nvec_msg_free(nvec, nvec->rx);
|
|
nvec->state = 0;
|
|
|
|
/* Battery quirk - Often incomplete, and likes to crash */
|
|
if (nvec->rx->data[0] == NVEC_BAT)
|
|
complete(&nvec->ec_transfer);
|
|
|
|
return;
|
|
}
|
|
|
|
spin_lock(&nvec->rx_lock);
|
|
|
|
/*
|
|
* Add the received data to the work list and move the ring buffer
|
|
* pointer to the next entry.
|
|
*/
|
|
list_add_tail(&nvec->rx->node, &nvec->rx_data);
|
|
|
|
spin_unlock(&nvec->rx_lock);
|
|
|
|
nvec->state = 0;
|
|
|
|
if (!nvec_msg_is_event(nvec->rx))
|
|
complete(&nvec->ec_transfer);
|
|
|
|
schedule_work(&nvec->rx_work);
|
|
}
|
|
|
|
/**
|
|
* nvec_invalid_flags - Send an error message about invalid flags and jump
|
|
* @nvec: The nvec device
|
|
* @status: The status flags
|
|
* @reset: Whether we shall jump to state 0.
|
|
*/
|
|
static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status,
|
|
bool reset)
|
|
{
|
|
dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n",
|
|
status, nvec->state);
|
|
if (reset)
|
|
nvec->state = 0;
|
|
}
|
|
|
|
/**
|
|
* nvec_tx_set - Set the message to transfer (nvec->tx)
|
|
* @nvec: A &struct nvec_chip
|
|
*
|
|
* Gets the first entry from the tx_data list of @nvec and sets the
|
|
* tx member to it. If the tx_data list is empty, this uses the
|
|
* tx_scratch message to send a no operation message.
|
|
*/
|
|
static void nvec_tx_set(struct nvec_chip *nvec)
|
|
{
|
|
spin_lock(&nvec->tx_lock);
|
|
if (list_empty(&nvec->tx_data)) {
|
|
dev_err(nvec->dev, "empty tx - sending no-op\n");
|
|
memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3);
|
|
nvec->tx_scratch.size = 3;
|
|
nvec->tx_scratch.pos = 0;
|
|
nvec->tx = &nvec->tx_scratch;
|
|
list_add_tail(&nvec->tx->node, &nvec->tx_data);
|
|
} else {
|
|
nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg,
|
|
node);
|
|
nvec->tx->pos = 0;
|
|
}
|
|
spin_unlock(&nvec->tx_lock);
|
|
|
|
dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n",
|
|
(uint)nvec->tx->size, nvec->tx->data[1]);
|
|
}
|
|
|
|
/**
|
|
* nvec_interrupt - Interrupt handler
|
|
* @irq: The IRQ
|
|
* @dev: The nvec device
|
|
*
|
|
* Interrupt handler that fills our RX buffers and empties our TX
|
|
* buffers. This uses a finite state machine with ridiculous amounts
|
|
* of error checking, in order to be fairly reliable.
|
|
*/
|
|
static irqreturn_t nvec_interrupt(int irq, void *dev)
|
|
{
|
|
unsigned long status;
|
|
unsigned int received = 0;
|
|
unsigned char to_send = 0xff;
|
|
const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW;
|
|
struct nvec_chip *nvec = dev;
|
|
unsigned int state = nvec->state;
|
|
|
|
status = readl(nvec->base + I2C_SL_STATUS);
|
|
|
|
/* Filter out some errors */
|
|
if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) {
|
|
dev_err(nvec->dev, "unexpected irq mask %lx\n", status);
|
|
return IRQ_HANDLED;
|
|
}
|
|
if ((status & I2C_SL_IRQ) == 0) {
|
|
dev_err(nvec->dev, "Spurious IRQ\n");
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/* The EC did not request a read, so it send us something, read it */
|
|
if ((status & RNW) == 0) {
|
|
received = readl(nvec->base + I2C_SL_RCVD);
|
|
if (status & RCVD)
|
|
writel(0, nvec->base + I2C_SL_RCVD);
|
|
}
|
|
|
|
if (status == (I2C_SL_IRQ | RCVD))
|
|
nvec->state = 0;
|
|
|
|
switch (nvec->state) {
|
|
case 0: /* Verify that its a transfer start, the rest later */
|
|
if (status != (I2C_SL_IRQ | RCVD))
|
|
nvec_invalid_flags(nvec, status, false);
|
|
break;
|
|
case 1: /* command byte */
|
|
if (status != I2C_SL_IRQ) {
|
|
nvec_invalid_flags(nvec, status, true);
|
|
} else {
|
|
nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX);
|
|
/* Should not happen in a normal world */
|
|
if (unlikely(!nvec->rx)) {
|
|
nvec->state = 0;
|
|
break;
|
|
}
|
|
nvec->rx->data[0] = received;
|
|
nvec->rx->pos = 1;
|
|
nvec->state = 2;
|
|
}
|
|
break;
|
|
case 2: /* first byte after command */
|
|
if (status == (I2C_SL_IRQ | RNW | RCVD)) {
|
|
udelay(33);
|
|
if (nvec->rx->data[0] != 0x01) {
|
|
dev_err(nvec->dev,
|
|
"Read without prior read command\n");
|
|
nvec->state = 0;
|
|
break;
|
|
}
|
|
nvec_msg_free(nvec, nvec->rx);
|
|
nvec->state = 3;
|
|
nvec_tx_set(nvec);
|
|
to_send = nvec->tx->data[0];
|
|
nvec->tx->pos = 1;
|
|
} else if (status == (I2C_SL_IRQ)) {
|
|
nvec->rx->data[1] = received;
|
|
nvec->rx->pos = 2;
|
|
nvec->state = 4;
|
|
} else {
|
|
nvec_invalid_flags(nvec, status, true);
|
|
}
|
|
break;
|
|
case 3: /* EC does a block read, we transmit data */
|
|
if (status & END_TRANS) {
|
|
nvec_tx_completed(nvec);
|
|
} else if ((status & RNW) == 0 || (status & RCVD)) {
|
|
nvec_invalid_flags(nvec, status, true);
|
|
} else if (nvec->tx && nvec->tx->pos < nvec->tx->size) {
|
|
to_send = nvec->tx->data[nvec->tx->pos++];
|
|
} else {
|
|
dev_err(nvec->dev,
|
|
"tx buffer underflow on %p (%u > %u)\n",
|
|
nvec->tx,
|
|
(uint)(nvec->tx ? nvec->tx->pos : 0),
|
|
(uint)(nvec->tx ? nvec->tx->size : 0));
|
|
nvec->state = 0;
|
|
}
|
|
break;
|
|
case 4: /* EC does some write, we read the data */
|
|
if ((status & (END_TRANS | RNW)) == END_TRANS)
|
|
nvec_rx_completed(nvec);
|
|
else if (status & (RNW | RCVD))
|
|
nvec_invalid_flags(nvec, status, true);
|
|
else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE)
|
|
nvec->rx->data[nvec->rx->pos++] = received;
|
|
else
|
|
dev_err(nvec->dev,
|
|
"RX buffer overflow on %p: Trying to write byte %u of %u\n",
|
|
nvec->rx, nvec->rx ? nvec->rx->pos : 0,
|
|
NVEC_MSG_SIZE);
|
|
break;
|
|
default:
|
|
nvec->state = 0;
|
|
}
|
|
|
|
/* If we are told that a new transfer starts, verify it */
|
|
if ((status & (RCVD | RNW)) == RCVD) {
|
|
if (received != nvec->i2c_addr)
|
|
dev_err(nvec->dev,
|
|
"received address 0x%02x, expected 0x%02x\n",
|
|
received, nvec->i2c_addr);
|
|
nvec->state = 1;
|
|
}
|
|
|
|
/* Send data if requested, but not on end of transmission */
|
|
if ((status & (RNW | END_TRANS)) == RNW)
|
|
writel(to_send, nvec->base + I2C_SL_RCVD);
|
|
|
|
/* If we have send the first byte */
|
|
if (status == (I2C_SL_IRQ | RNW | RCVD))
|
|
nvec_gpio_set_value(nvec, 1);
|
|
|
|
dev_dbg(nvec->dev,
|
|
"Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n",
|
|
(status & RNW) == 0 ? "received" : "R=",
|
|
received,
|
|
(status & (RNW | END_TRANS)) ? "sent" : "S=",
|
|
to_send,
|
|
state,
|
|
status & END_TRANS ? " END_TRANS" : "",
|
|
status & RCVD ? " RCVD" : "",
|
|
status & RNW ? " RNW" : "");
|
|
|
|
/*
|
|
* TODO: A correct fix needs to be found for this.
|
|
*
|
|
* We experience less incomplete messages with this delay than without
|
|
* it, but we don't know why. Help is appreciated.
|
|
*/
|
|
udelay(100);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void tegra_init_i2c_slave(struct nvec_chip *nvec)
|
|
{
|
|
u32 val;
|
|
|
|
clk_prepare_enable(nvec->i2c_clk);
|
|
|
|
reset_control_assert(nvec->rst);
|
|
udelay(2);
|
|
reset_control_deassert(nvec->rst);
|
|
|
|
val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
|
|
(0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
|
|
writel(val, nvec->base + I2C_CNFG);
|
|
|
|
clk_set_rate(nvec->i2c_clk, 8 * 80000);
|
|
|
|
writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG);
|
|
writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT);
|
|
|
|
writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1);
|
|
writel(0, nvec->base + I2C_SL_ADDR2);
|
|
|
|
enable_irq(nvec->irq);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static void nvec_disable_i2c_slave(struct nvec_chip *nvec)
|
|
{
|
|
disable_irq(nvec->irq);
|
|
writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG);
|
|
clk_disable_unprepare(nvec->i2c_clk);
|
|
}
|
|
#endif
|
|
|
|
static void nvec_power_off(void)
|
|
{
|
|
char ap_pwr_down[] = { NVEC_SLEEP, AP_PWR_DOWN };
|
|
|
|
nvec_toggle_global_events(nvec_power_handle, false);
|
|
nvec_write_async(nvec_power_handle, ap_pwr_down, 2);
|
|
}
|
|
|
|
/*
|
|
* Parse common device tree data
|
|
*/
|
|
static int nvec_i2c_parse_dt_pdata(struct nvec_chip *nvec)
|
|
{
|
|
nvec->gpio = of_get_named_gpio(nvec->dev->of_node, "request-gpios", 0);
|
|
|
|
if (nvec->gpio < 0) {
|
|
dev_err(nvec->dev, "no gpio specified");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (of_property_read_u32(nvec->dev->of_node, "slave-addr",
|
|
&nvec->i2c_addr)) {
|
|
dev_err(nvec->dev, "no i2c address specified");
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_nvec_probe(struct platform_device *pdev)
|
|
{
|
|
int err, ret;
|
|
struct clk *i2c_clk;
|
|
struct nvec_chip *nvec;
|
|
struct nvec_msg *msg;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
char get_firmware_version[] = { NVEC_CNTL, GET_FIRMWARE_VERSION },
|
|
unmute_speakers[] = { NVEC_OEM0, 0x10, 0x59, 0x95 },
|
|
enable_event[7] = { NVEC_SYS, CNF_EVENT_REPORTING, true };
|
|
|
|
if (!pdev->dev.of_node) {
|
|
dev_err(&pdev->dev, "must be instantiated using device tree\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
nvec = devm_kzalloc(&pdev->dev, sizeof(struct nvec_chip), GFP_KERNEL);
|
|
if (!nvec)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, nvec);
|
|
nvec->dev = &pdev->dev;
|
|
|
|
err = nvec_i2c_parse_dt_pdata(nvec);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
nvec->irq = platform_get_irq(pdev, 0);
|
|
if (nvec->irq < 0) {
|
|
dev_err(&pdev->dev, "no irq resource?\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
i2c_clk = devm_clk_get(&pdev->dev, "div-clk");
|
|
if (IS_ERR(i2c_clk)) {
|
|
dev_err(nvec->dev, "failed to get controller clock\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
nvec->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
|
|
if (IS_ERR(nvec->rst)) {
|
|
dev_err(nvec->dev, "failed to get controller reset\n");
|
|
return PTR_ERR(nvec->rst);
|
|
}
|
|
|
|
nvec->base = base;
|
|
nvec->i2c_clk = i2c_clk;
|
|
nvec->rx = &nvec->msg_pool[0];
|
|
|
|
ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list);
|
|
|
|
init_completion(&nvec->sync_write);
|
|
init_completion(&nvec->ec_transfer);
|
|
mutex_init(&nvec->sync_write_mutex);
|
|
spin_lock_init(&nvec->tx_lock);
|
|
spin_lock_init(&nvec->rx_lock);
|
|
INIT_LIST_HEAD(&nvec->rx_data);
|
|
INIT_LIST_HEAD(&nvec->tx_data);
|
|
INIT_WORK(&nvec->rx_work, nvec_dispatch);
|
|
INIT_WORK(&nvec->tx_work, nvec_request_master);
|
|
|
|
err = devm_gpio_request_one(&pdev->dev, nvec->gpio, GPIOF_OUT_INIT_HIGH,
|
|
"nvec gpio");
|
|
if (err < 0) {
|
|
dev_err(nvec->dev, "couldn't request gpio\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
err = devm_request_irq(&pdev->dev, nvec->irq, nvec_interrupt, 0,
|
|
"nvec", nvec);
|
|
if (err) {
|
|
dev_err(nvec->dev, "couldn't request irq\n");
|
|
return -ENODEV;
|
|
}
|
|
disable_irq(nvec->irq);
|
|
|
|
tegra_init_i2c_slave(nvec);
|
|
|
|
/* enable event reporting */
|
|
nvec_toggle_global_events(nvec, true);
|
|
|
|
nvec->nvec_status_notifier.notifier_call = nvec_status_notifier;
|
|
nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0);
|
|
|
|
nvec_power_handle = nvec;
|
|
pm_power_off = nvec_power_off;
|
|
|
|
/* Get Firmware Version */
|
|
err = nvec_write_sync(nvec, get_firmware_version, 2, &msg);
|
|
|
|
if (!err) {
|
|
dev_warn(nvec->dev,
|
|
"ec firmware version %02x.%02x.%02x / %02x\n",
|
|
msg->data[4], msg->data[5],
|
|
msg->data[6], msg->data[7]);
|
|
|
|
nvec_msg_free(nvec, msg);
|
|
}
|
|
|
|
ret = mfd_add_devices(nvec->dev, 0, nvec_devices,
|
|
ARRAY_SIZE(nvec_devices), NULL, 0, NULL);
|
|
if (ret)
|
|
dev_err(nvec->dev, "error adding subdevices\n");
|
|
|
|
/* unmute speakers? */
|
|
nvec_write_async(nvec, unmute_speakers, 4);
|
|
|
|
/* enable lid switch event */
|
|
nvec_event_mask(enable_event, LID_SWITCH);
|
|
nvec_write_async(nvec, enable_event, 7);
|
|
|
|
/* enable power button event */
|
|
nvec_event_mask(enable_event, PWR_BUTTON);
|
|
nvec_write_async(nvec, enable_event, 7);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_nvec_remove(struct platform_device *pdev)
|
|
{
|
|
struct nvec_chip *nvec = platform_get_drvdata(pdev);
|
|
|
|
nvec_toggle_global_events(nvec, false);
|
|
mfd_remove_devices(nvec->dev);
|
|
nvec_unregister_notifier(nvec, &nvec->nvec_status_notifier);
|
|
cancel_work_sync(&nvec->rx_work);
|
|
cancel_work_sync(&nvec->tx_work);
|
|
/* FIXME: needs check whether nvec is responsible for power off */
|
|
pm_power_off = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int nvec_suspend(struct device *dev)
|
|
{
|
|
int err;
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct nvec_chip *nvec = platform_get_drvdata(pdev);
|
|
struct nvec_msg *msg;
|
|
char ap_suspend[] = { NVEC_SLEEP, AP_SUSPEND };
|
|
|
|
dev_dbg(nvec->dev, "suspending\n");
|
|
|
|
/* keep these sync or you'll break suspend */
|
|
nvec_toggle_global_events(nvec, false);
|
|
|
|
err = nvec_write_sync(nvec, ap_suspend, sizeof(ap_suspend), &msg);
|
|
if (!err)
|
|
nvec_msg_free(nvec, msg);
|
|
|
|
nvec_disable_i2c_slave(nvec);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nvec_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct nvec_chip *nvec = platform_get_drvdata(pdev);
|
|
|
|
dev_dbg(nvec->dev, "resuming\n");
|
|
tegra_init_i2c_slave(nvec);
|
|
nvec_toggle_global_events(nvec, true);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume);
|
|
|
|
/* Match table for of_platform binding */
|
|
static const struct of_device_id nvidia_nvec_of_match[] = {
|
|
{ .compatible = "nvidia,nvec", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match);
|
|
|
|
static struct platform_driver nvec_device_driver = {
|
|
.probe = tegra_nvec_probe,
|
|
.remove = tegra_nvec_remove,
|
|
.driver = {
|
|
.name = "nvec",
|
|
.pm = &nvec_pm_ops,
|
|
.of_match_table = nvidia_nvec_of_match,
|
|
}
|
|
};
|
|
|
|
module_platform_driver(nvec_device_driver);
|
|
|
|
MODULE_ALIAS("platform:nvec");
|
|
MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface");
|
|
MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>");
|
|
MODULE_LICENSE("GPL");
|