![Linus Torvalds](/assets/img/avatar_default.png)
General updates: * Constify pci_device_id in various drivers * Constify device_type * Remove pad control code from the Gemini driver * Use %pOF to print OF node full_name * Various fixes in the physmap_of driver * Remove unused vars in mtdswap * Check devm_kzalloc() return value in the spear_smi driver * Check clk_prepare_enable() return code in the st_spi_fsm driver * Create per MTD device debugfs enties NAND updates, from Boris Brezillon: * Fix memory leaks in the core * Remove unused NAND locking support * Rename nand.h into rawnand.h (preparing support for spi NANDs) * Use NAND_MAX_ID_LEN where appropriate * Fix support for 20nm Hynix chips * Fix support for Samsung and Hynix SLC NANDs * Various cleanup, improvements and fixes in the qcom driver * Fixes for bugs detected by various static code analysis tools * Fix mxc ooblayout definition * Add a new part_parsers to tmio and sharpsl platform data in order to define a custom list of partition parsers * Request the reset line in exclusive mode in the sunxi driver * Fix a build error in the orion-nand driver when compiled for ARMv4 * Allow 64-bit mvebu platforms to select the PXA3XX driver SPI NOR updates, from Cyrille Pitchen and Marek Vasut: * add support to the JEDEC JESD216B specification (SFDP tables). * add support to the Intel Denverton SPI flash controller. * fix error recovery for Spansion/Cypress SPI NOR memories. * fix 4-byte address management for the Aspeed SPI controller. * add support to some Microchip SST26 memory parts * remove unneeded pinctrl header Write a message for tag: -----BEGIN PGP SIGNATURE----- iQJABAABCAAqBQJZrav6Ixxib3Jpcy5icmV6aWxsb25AZnJlZS1lbGVjdHJvbnMu Y29tAAoJEGXtNgF+CLcABwkP/joDrq09RIC9n5gP+ubJe6O1jKvNWDd6bIVXD3Ke 73R0a0ANwwWlNYWTChTdrb8UeewVS1bzutyy5O2Sbdb6Jc6s7xkfQDTsbET2HWOK S7Lt/zjlC6/6cow59B6h43PGS6wmIFaZD3K+70sGhvFnV8epVUzS2Aa783xS8LXm so2djZOdUYnW+yE0eho24VQR6nS4YP4Vc+7Mm9skjU0ifjB9mJiWRkzoQnqIgORO M+Iab+qjDs9KR/edWh6mZtnvjps0VSW4I40YsClpcgIn550w1DSXe4u6/8Nk+2Bp gfrALls91gob0ocxmEdIyLID+M0410HcN/Lvh36nw+tkkGTaXf0D6mkqzdKNrZ3w yz+UV9uf19kr1c6zFGcCvUlD0btn9KT+F2legnhgURtwUyDFQcaYQlkpDIeEzUMV ZrtzKbSE2v9810YKXjtCnseewdP+Eph/ewN6ODX5yg/fs8K0fyQYTRtYYM50U69X md8zznBBDPhJVu5T2Of7my9V1SxvCP8a7LrKjAXuFHpZ/CHiPe+QOWBgG2L+zXXT e10/rTg7T2pcyKpBvL/3/mCYeJ+Iup3lKT1EHGCXcKnLGecVgOsbvdG+JnvQMI2J FLmu1exvrzi0Gcrs/05hqwyUvkHZ5FB1a+heNOtmQ+h1U0ElXqILyu7brzghupRe 3phO =UgCd -----END PGP SIGNATURE----- Merge tag 'for-linus-20170904' of git://git.infradead.org/linux-mtd Pull MTD updates from Boris Brezillon: "General updates: - Constify pci_device_id in various drivers - Constify device_type - Remove pad control code from the Gemini driver - Use %pOF to print OF node full_name - Various fixes in the physmap_of driver - Remove unused vars in mtdswap - Check devm_kzalloc() return value in the spear_smi driver - Check clk_prepare_enable() return code in the st_spi_fsm driver - Create per MTD device debugfs enties NAND updates, from Boris Brezillon: - Fix memory leaks in the core - Remove unused NAND locking support - Rename nand.h into rawnand.h (preparing support for spi NANDs) - Use NAND_MAX_ID_LEN where appropriate - Fix support for 20nm Hynix chips - Fix support for Samsung and Hynix SLC NANDs - Various cleanup, improvements and fixes in the qcom driver - Fixes for bugs detected by various static code analysis tools - Fix mxc ooblayout definition - Add a new part_parsers to tmio and sharpsl platform data in order to define a custom list of partition parsers - Request the reset line in exclusive mode in the sunxi driver - Fix a build error in the orion-nand driver when compiled for ARMv4 - Allow 64-bit mvebu platforms to select the PXA3XX driver SPI NOR updates, from Cyrille Pitchen and Marek Vasut: - add support to the JEDEC JESD216B specification (SFDP tables). - add support to the Intel Denverton SPI flash controller. - fix error recovery for Spansion/Cypress SPI NOR memories. - fix 4-byte address management for the Aspeed SPI controller. - add support to some Microchip SST26 memory parts - remove unneeded pinctrl header Write a message for tag:" * tag 'for-linus-20170904' of git://git.infradead.org/linux-mtd: (74 commits) mtd: nand: complain loudly when chip->bits_per_cell is not correctly initialized mtd: nand: make Samsung SLC NAND usable again mtd: nand: tmio: Register partitions using the parsers mfd: tmio: Add partition parsers platform data mtd: nand: sharpsl: Register partitions using the parsers mtd: nand: sharpsl: Add partition parsers platform data mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller mtd: nand: qcom: support for IPQ4019 QPIC NAND controller dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation dt-bindings: qcom_nandc: fix the ipq806x device tree example mtd: nand: qcom: support for different DEV_CMD register offsets mtd: nand: qcom: QPIC data descriptors handling mtd: nand: qcom: enable BAM or ADM mode mtd: nand: qcom: erased codeword detection configuration mtd: nand: qcom: support for read location registers mtd: nand: qcom: support for passing flags in DMA helper functions mtd: nand: qcom: add BAM DMA descriptor handling mtd: nand: qcom: allocate BAM transaction mtd: nand: qcom: DMA mapping support for register read buffer ...
167 lines
4.6 KiB
C
167 lines
4.6 KiB
C
#ifndef MFD_TMIO_H
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#define MFD_TMIO_H
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#include <linux/device.h>
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#include <linux/fb.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/mmc/card.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#define tmio_ioread8(addr) readb(addr)
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#define tmio_ioread16(addr) readw(addr)
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#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
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#define tmio_ioread32(addr) \
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(((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
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#define tmio_iowrite8(val, addr) writeb((val), (addr))
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#define tmio_iowrite16(val, addr) writew((val), (addr))
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#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
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#define tmio_iowrite32(val, addr) \
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do { \
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writew((val), (addr)); \
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writew((val) >> 16, (addr) + 2); \
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} while (0)
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#define CNF_CMD 0x04
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#define CNF_CTL_BASE 0x10
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#define CNF_INT_PIN 0x3d
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#define CNF_STOP_CLK_CTL 0x40
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#define CNF_GCLK_CTL 0x41
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#define CNF_SD_CLK_MODE 0x42
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#define CNF_PIN_STATUS 0x44
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#define CNF_PWR_CTL_1 0x48
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#define CNF_PWR_CTL_2 0x49
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#define CNF_PWR_CTL_3 0x4a
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#define CNF_CARD_DETECT_MODE 0x4c
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#define CNF_SD_SLOT 0x50
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#define CNF_EXT_GCLK_CTL_1 0xf0
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#define CNF_EXT_GCLK_CTL_2 0xf1
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#define CNF_EXT_GCLK_CTL_3 0xf9
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#define CNF_SD_LED_EN_1 0xfa
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#define CNF_SD_LED_EN_2 0xfe
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#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
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#define sd_config_write8(base, shift, reg, val) \
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tmio_iowrite8((val), (base) + ((reg) << (shift)))
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#define sd_config_write16(base, shift, reg, val) \
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tmio_iowrite16((val), (base) + ((reg) << (shift)))
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#define sd_config_write32(base, shift, reg, val) \
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do { \
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tmio_iowrite16((val), (base) + ((reg) << (shift))); \
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tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
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} while (0)
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/* tmio MMC platform flags */
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#define TMIO_MMC_WRPROTECT_DISABLE BIT(0)
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/*
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* Some controllers can support a 2-byte block size when the bus width
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* is configured in 4-bit mode.
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*/
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#define TMIO_MMC_BLKSZ_2BYTES BIT(1)
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/*
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* Some controllers can support SDIO IRQ signalling.
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*/
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#define TMIO_MMC_SDIO_IRQ BIT(2)
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/* Some features are only available or tested on R-Car Gen2 or later */
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#define TMIO_MMC_MIN_RCAR2 BIT(3)
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/*
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* Some controllers require waiting for the SD bus to become
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* idle before writing to some registers.
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*/
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#define TMIO_MMC_HAS_IDLE_WAIT BIT(4)
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/*
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* A GPIO is used for card hotplug detection. We need an extra flag for this,
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* because 0 is a valid GPIO number too, and requiring users to specify
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* cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
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*/
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#define TMIO_MMC_USE_GPIO_CD BIT(5)
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/*
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* Some controllers doesn't have over 0x100 register.
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* it is used to checking accessibility of
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* CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
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*/
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#define TMIO_MMC_HAVE_HIGH_REG BIT(6)
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/*
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* Some controllers have CMD12 automatically
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* issue/non-issue register
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*/
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#define TMIO_MMC_HAVE_CMD12_CTRL BIT(7)
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/* Controller has some SDIO status bits which must be 1 */
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#define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8)
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/*
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* Some controllers have a 32-bit wide data port register
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*/
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#define TMIO_MMC_32BIT_DATA_PORT BIT(9)
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/*
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* Some controllers allows to set SDx actual clock
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*/
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#define TMIO_MMC_CLK_ACTUAL BIT(10)
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/* Some controllers have a CBSY bit */
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#define TMIO_MMC_HAVE_CBSY BIT(11)
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
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struct dma_chan;
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/*
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* data for the MMC controller
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*/
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struct tmio_mmc_data {
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void *chan_priv_tx;
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void *chan_priv_rx;
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unsigned int hclk;
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unsigned long capabilities;
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unsigned long capabilities2;
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unsigned long flags;
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u32 ocr_mask; /* available voltages */
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unsigned int cd_gpio;
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int alignment_shift;
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dma_addr_t dma_rx_offset;
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unsigned int max_blk_count;
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unsigned short max_segs;
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void (*set_pwr)(struct platform_device *host, int state);
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void (*set_clk_div)(struct platform_device *host, int state);
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};
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/*
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* data for the NAND controller
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*/
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struct tmio_nand_data {
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struct nand_bbt_descr *badblock_pattern;
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struct mtd_partition *partition;
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unsigned int num_partitions;
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const char *const *part_parsers;
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};
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#define FBIO_TMIO_ACC_WRITE 0x7C639300
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#define FBIO_TMIO_ACC_SYNC 0x7C639301
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struct tmio_fb_data {
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int (*lcd_set_power)(struct platform_device *fb_dev,
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bool on);
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int (*lcd_mode)(struct platform_device *fb_dev,
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const struct fb_videomode *mode);
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int num_modes;
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struct fb_videomode *modes;
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/* in mm: size of screen */
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int height;
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int width;
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};
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#endif
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