01c3207091
This patch replaces the local includes with the global header. So the the crystalhd.h will be the only header included by the other files. Signed-off-by: Jorgyano Vieira <jorgyano@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
298 lines
8.5 KiB
C
298 lines
8.5 KiB
C
/********************************************************************
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* Copyright(c) 2006-2009 Broadcom Corporation.
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*
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* Name: bc_dts_glob_lnx.h
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*
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* Description: Wrapper to Windows dts_glob.h for Link-Linux usage.
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* The idea is to define additional Linux related defs
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* in this file to avoid changes to existing Windows
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* glob file.
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*
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* AU
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*
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* HISTORY:
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*
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********************************************************************
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* This header is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published
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* by the Free Software Foundation, either version 2.1 of the License.
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*
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* This header is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public License
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* along with this header. If not, see <http://www.gnu.org/licenses/>.
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*******************************************************************/
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#ifndef _BC_DTS_GLOB_LNX_H_
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#define _BC_DTS_GLOB_LNX_H_
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#ifdef __LINUX_USER__
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <ctype.h>
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#include <string.h>
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#include <errno.h>
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#include <netdb.h>
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#include <sys/time.h>
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#include <time.h>
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#include <arpa/inet.h>
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#include <linux/param.h>
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#include <linux/ioctl.h>
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#include <sys/select.h>
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#define DRVIFLIB_INT_API
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#endif
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#include "crystalhd.h"
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#define CRYSTALHD_API_NAME "crystalhd"
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#define CRYSTALHD_API_DEV_NAME "/dev/crystalhd"
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/*
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* These are SW stack tunable parameters shared
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* between the driver and the application.
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*/
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enum BC_DTS_GLOBALS {
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BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */
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PCI_CFG_SIZE = 256, /* PCI config size buffer */
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BC_IOCTL_DATA_POOL_SIZE = 8, /* BC_IOCTL_DATA Pool size */
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BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/
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BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */
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BC_TX_LIST_CNT = 2, /* Max Tx DMA Rings */
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BC_RX_LIST_CNT = 8, /* Max Rx DMA Rings*/
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BC_PROC_OUTPUT_TIMEOUT = 3000, /* Milliseconds */
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BC_INFIFO_THRESHOLD = 0x10000,
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};
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struct BC_CMD_REG_ACC {
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uint32_t Offset;
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uint32_t Value;
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};
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struct BC_CMD_DEV_MEM {
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uint32_t StartOff;
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uint32_t NumDwords;
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uint32_t Rsrd;
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};
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/* FW Passthrough command structure */
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enum bc_fw_cmd_flags {
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BC_FW_CMD_FLAGS_NONE = 0,
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BC_FW_CMD_PIB_QS = 0x01,
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};
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struct BC_FW_CMD {
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uint32_t cmd[BC_MAX_FW_CMD_BUFF_SZ];
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uint32_t rsp[BC_MAX_FW_CMD_BUFF_SZ];
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uint32_t flags;
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uint32_t add_data;
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};
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struct BC_HW_TYPE {
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uint16_t PciDevId;
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uint16_t PciVenId;
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uint8_t HwRev;
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uint8_t Align[3];
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};
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struct BC_PCI_CFG {
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uint32_t Size;
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uint32_t Offset;
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uint8_t pci_cfg_space[PCI_CFG_SIZE];
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};
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struct BC_VERSION_INFO {
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uint8_t DriverMajor;
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uint8_t DriverMinor;
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uint16_t DriverRevision;
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};
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struct BC_START_RX_CAP {
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uint32_t Rsrd;
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uint32_t StartDeliveryThsh;
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uint32_t PauseThsh;
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uint32_t ResumeThsh;
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};
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struct BC_FLUSH_RX_CAP {
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uint32_t Rsrd;
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uint32_t bDiscardOnly;
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};
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struct BC_DTS_STATS {
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uint8_t drvRLL;
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uint8_t drvFLL;
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uint8_t eosDetected;
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uint8_t pwr_state_change;
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/* Stats from App */
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uint32_t opFrameDropped;
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uint32_t opFrameCaptured;
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uint32_t ipSampleCnt;
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uint64_t ipTotalSize;
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uint32_t reptdFrames;
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uint32_t pauseCount;
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uint32_t pibMisses;
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uint32_t discCounter;
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/* Stats from Driver */
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uint32_t TxFifoBsyCnt;
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uint32_t intCount;
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uint32_t DrvIgnIntrCnt;
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uint32_t DrvTotalFrmDropped;
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uint32_t DrvTotalHWErrs;
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uint32_t DrvTotalPIBFlushCnt;
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uint32_t DrvTotalFrmCaptured;
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uint32_t DrvPIBMisses;
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uint32_t DrvPauseTime;
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uint32_t DrvRepeatedFrms;
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uint32_t res1[13];
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};
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struct BC_PROC_INPUT {
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uint8_t *pDmaBuff;
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uint32_t BuffSz;
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uint8_t Mapped;
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uint8_t Encrypted;
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uint8_t Rsrd[2];
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uint32_t DramOffset; /* For debug use only */
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};
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struct BC_DEC_YUV_BUFFS {
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uint32_t b422Mode;
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uint8_t *YuvBuff;
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uint32_t YuvBuffSz;
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uint32_t UVbuffOffset;
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uint32_t YBuffDoneSz;
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uint32_t UVBuffDoneSz;
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uint32_t RefCnt;
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};
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enum DECOUT_COMPLETION_FLAGS {
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COMP_FLAG_NO_INFO = 0x00,
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COMP_FLAG_FMT_CHANGE = 0x01,
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COMP_FLAG_PIB_VALID = 0x02,
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COMP_FLAG_DATA_VALID = 0x04,
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COMP_FLAG_DATA_ENC = 0x08,
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COMP_FLAG_DATA_BOT = 0x10,
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};
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struct BC_DEC_OUT_BUFF {
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struct BC_DEC_YUV_BUFFS OutPutBuffs;
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struct BC_PIC_INFO_BLOCK PibInfo;
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uint32_t Flags;
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uint32_t BadFrCnt;
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};
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struct BC_NOTIFY_MODE {
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uint32_t Mode;
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uint32_t Rsvr[3];
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};
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struct BC_CLOCK {
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uint32_t clk;
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uint32_t Rsvr[3];
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};
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struct BC_IOCTL_DATA {
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enum BC_STATUS RetSts;
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uint32_t IoctlDataSz;
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uint32_t Timeout;
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union {
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struct BC_CMD_REG_ACC regAcc;
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struct BC_CMD_DEV_MEM devMem;
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struct BC_FW_CMD fwCmd;
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struct BC_HW_TYPE hwType;
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struct BC_PCI_CFG pciCfg;
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struct BC_VERSION_INFO VerInfo;
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struct BC_PROC_INPUT ProcInput;
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struct BC_DEC_YUV_BUFFS RxBuffs;
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struct BC_DEC_OUT_BUFF DecOutData;
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struct BC_START_RX_CAP RxCap;
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struct BC_FLUSH_RX_CAP FlushRxCap;
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struct BC_DTS_STATS drvStat;
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struct BC_NOTIFY_MODE NotifyMode;
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struct BC_CLOCK clockValue;
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} u;
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struct _BC_IOCTL_DATA *next;
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};
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enum BC_DRV_CMD {
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DRV_CMD_VERSION = 0, /* Get SW version */
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DRV_CMD_GET_HWTYPE, /* Get HW version and type Dozer/Tank */
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DRV_CMD_REG_RD, /* Read Device Register */
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DRV_CMD_REG_WR, /* Write Device Register */
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DRV_CMD_FPGA_RD, /* Read FPGA Register */
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DRV_CMD_FPGA_WR, /* Wrtie FPGA Reister */
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DRV_CMD_MEM_RD, /* Read Device Memory */
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DRV_CMD_MEM_WR, /* Write Device Memory */
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DRV_CMD_RD_PCI_CFG, /* Read PCI Config Space */
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DRV_CMD_WR_PCI_CFG, /* Write the PCI Configuration Space*/
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DRV_CMD_FW_DOWNLOAD, /* Download Firmware */
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DRV_ISSUE_FW_CMD, /* Issue FW Cmd (pass through mode) */
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DRV_CMD_PROC_INPUT, /* Process Input Sample */
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DRV_CMD_ADD_RXBUFFS, /* Add Rx side buffers to driver pool */
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DRV_CMD_FETCH_RXBUFF, /* Get Rx DMAed buffer */
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DRV_CMD_START_RX_CAP, /* Start Rx Buffer Capture */
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DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now...we will enhance this later*/
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DRV_CMD_GET_DRV_STAT, /* Get Driver Internal Statistics */
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DRV_CMD_RST_DRV_STAT, /* Reset Driver Internal Statistics */
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DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver in which the application is Operating*/
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DRV_CMD_CHANGE_CLOCK, /* Change the core clock to either save power or improve performance */
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/* MUST be the last one.. */
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DRV_CMD_END, /* End of the List.. */
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};
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#define BC_IOC_BASE 'b'
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#define BC_IOC_VOID _IOC_NONE
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#define BC_IOC_IOWR(nr, type) _IOWR(BC_IOC_BASE, nr, type)
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#define BC_IOCTL_MB struct BC_IOCTL_DATA
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#define BCM_IOC_GET_VERSION BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB)
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#define BCM_IOC_GET_HWTYPE BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB)
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#define BCM_IOC_REG_RD BC_IOC_IOWR(DRV_CMD_REG_RD, BC_IOCTL_MB)
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#define BCM_IOC_REG_WR BC_IOC_IOWR(DRV_CMD_REG_WR, BC_IOCTL_MB)
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#define BCM_IOC_MEM_RD BC_IOC_IOWR(DRV_CMD_MEM_RD, BC_IOCTL_MB)
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#define BCM_IOC_MEM_WR BC_IOC_IOWR(DRV_CMD_MEM_WR, BC_IOCTL_MB)
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#define BCM_IOC_FPGA_RD BC_IOC_IOWR(DRV_CMD_FPGA_RD, BC_IOCTL_MB)
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#define BCM_IOC_FPGA_WR BC_IOC_IOWR(DRV_CMD_FPGA_WR, BC_IOCTL_MB)
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#define BCM_IOC_RD_PCI_CFG BC_IOC_IOWR(DRV_CMD_RD_PCI_CFG, BC_IOCTL_MB)
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#define BCM_IOC_WR_PCI_CFG BC_IOC_IOWR(DRV_CMD_WR_PCI_CFG, BC_IOCTL_MB)
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#define BCM_IOC_PROC_INPUT BC_IOC_IOWR(DRV_CMD_PROC_INPUT, BC_IOCTL_MB)
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#define BCM_IOC_ADD_RXBUFFS BC_IOC_IOWR(DRV_CMD_ADD_RXBUFFS, BC_IOCTL_MB)
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#define BCM_IOC_FETCH_RXBUFF BC_IOC_IOWR(DRV_CMD_FETCH_RXBUFF, BC_IOCTL_MB)
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#define BCM_IOC_FW_CMD BC_IOC_IOWR(DRV_ISSUE_FW_CMD, BC_IOCTL_MB)
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#define BCM_IOC_START_RX_CAP BC_IOC_IOWR(DRV_CMD_START_RX_CAP, BC_IOCTL_MB)
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#define BCM_IOC_FLUSH_RX_CAP BC_IOC_IOWR(DRV_CMD_FLUSH_RX_CAP, BC_IOCTL_MB)
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#define BCM_IOC_GET_DRV_STAT BC_IOC_IOWR(DRV_CMD_GET_DRV_STAT, BC_IOCTL_MB)
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#define BCM_IOC_RST_DRV_STAT BC_IOC_IOWR(DRV_CMD_RST_DRV_STAT, BC_IOCTL_MB)
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#define BCM_IOC_NOTIFY_MODE BC_IOC_IOWR(DRV_CMD_NOTIFY_MODE, BC_IOCTL_MB)
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#define BCM_IOC_FW_DOWNLOAD BC_IOC_IOWR(DRV_CMD_FW_DOWNLOAD, BC_IOCTL_MB)
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#define BCM_IOC_CHG_CLK BC_IOC_IOWR(DRV_CMD_CHANGE_CLOCK, BC_IOCTL_MB)
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#define BCM_IOC_END BC_IOC_VOID
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/* Wrapper for main IOCTL data */
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struct crystalhd_ioctl_data {
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struct BC_IOCTL_DATA udata; /* IOCTL from App..*/
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uint32_t u_id; /* Driver specific user ID */
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uint32_t cmd; /* Cmd ID for driver's use. */
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void *add_cdata; /* Additional command specific data..*/
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uint32_t add_cdata_sz; /* Additional command specific data size */
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struct crystalhd_ioctl_data *next; /* List/Fifo management */
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};
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enum crystalhd_kmod_ver {
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crystalhd_kmod_major = 0,
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crystalhd_kmod_minor = 9,
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crystalhd_kmod_rev = 27,
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};
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#endif
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