5a79859ae0
Remove the 31 bit support in order to reduce maintenance cost and
effectively remove dead code. Since a couple of years there is no
distribution left that comes with a 31 bit kernel.
The 31 bit kernel also has been broken since more than a year before
anybody noticed. In addition I added a removal warning to the kernel
shown at ipl for 5 minutes: a960062e58 ("s390: add 31 bit warning
message") which let everybody know about the plan to remove 31 bit
code. We didn't get any response.
Given that the last 31 bit only machine was introduced in 1999 let's
remove the code.
Anybody with 31 bit user space code can still use the compat mode.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
176 lines
4.4 KiB
C
176 lines
4.4 KiB
C
/*
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* Copyright IBM Corp. 1999, 2009
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef __ASM_SWITCH_TO_H
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#define __ASM_SWITCH_TO_H
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#include <linux/thread_info.h>
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#include <asm/ptrace.h>
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extern struct task_struct *__switch_to(void *, void *);
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extern void update_cr_regs(struct task_struct *task);
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static inline int test_fp_ctl(u32 fpc)
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{
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u32 orig_fpc;
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int rc;
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asm volatile(
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" efpc %1\n"
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" sfpc %2\n"
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"0: sfpc %1\n"
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" la %0,0\n"
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"1:\n"
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EX_TABLE(0b,1b)
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: "=d" (rc), "=d" (orig_fpc)
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: "d" (fpc), "0" (-EINVAL));
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return rc;
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}
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static inline void save_fp_ctl(u32 *fpc)
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{
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asm volatile(
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" stfpc %0\n"
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: "+Q" (*fpc));
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}
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static inline int restore_fp_ctl(u32 *fpc)
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{
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int rc;
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asm volatile(
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" lfpc %1\n"
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"0: la %0,0\n"
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"1:\n"
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EX_TABLE(0b,1b)
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: "=d" (rc) : "Q" (*fpc), "0" (-EINVAL));
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return rc;
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}
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static inline void save_fp_regs(freg_t *fprs)
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{
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asm volatile("std 0,%0" : "=Q" (fprs[0]));
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asm volatile("std 2,%0" : "=Q" (fprs[2]));
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asm volatile("std 4,%0" : "=Q" (fprs[4]));
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asm volatile("std 6,%0" : "=Q" (fprs[6]));
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asm volatile("std 1,%0" : "=Q" (fprs[1]));
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asm volatile("std 3,%0" : "=Q" (fprs[3]));
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asm volatile("std 5,%0" : "=Q" (fprs[5]));
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asm volatile("std 7,%0" : "=Q" (fprs[7]));
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asm volatile("std 8,%0" : "=Q" (fprs[8]));
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asm volatile("std 9,%0" : "=Q" (fprs[9]));
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asm volatile("std 10,%0" : "=Q" (fprs[10]));
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asm volatile("std 11,%0" : "=Q" (fprs[11]));
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asm volatile("std 12,%0" : "=Q" (fprs[12]));
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asm volatile("std 13,%0" : "=Q" (fprs[13]));
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asm volatile("std 14,%0" : "=Q" (fprs[14]));
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asm volatile("std 15,%0" : "=Q" (fprs[15]));
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}
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static inline void restore_fp_regs(freg_t *fprs)
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{
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asm volatile("ld 0,%0" : : "Q" (fprs[0]));
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asm volatile("ld 2,%0" : : "Q" (fprs[2]));
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asm volatile("ld 4,%0" : : "Q" (fprs[4]));
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asm volatile("ld 6,%0" : : "Q" (fprs[6]));
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asm volatile("ld 1,%0" : : "Q" (fprs[1]));
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asm volatile("ld 3,%0" : : "Q" (fprs[3]));
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asm volatile("ld 5,%0" : : "Q" (fprs[5]));
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asm volatile("ld 7,%0" : : "Q" (fprs[7]));
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asm volatile("ld 8,%0" : : "Q" (fprs[8]));
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asm volatile("ld 9,%0" : : "Q" (fprs[9]));
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asm volatile("ld 10,%0" : : "Q" (fprs[10]));
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asm volatile("ld 11,%0" : : "Q" (fprs[11]));
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asm volatile("ld 12,%0" : : "Q" (fprs[12]));
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asm volatile("ld 13,%0" : : "Q" (fprs[13]));
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asm volatile("ld 14,%0" : : "Q" (fprs[14]));
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asm volatile("ld 15,%0" : : "Q" (fprs[15]));
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}
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static inline void save_vx_regs(__vector128 *vxrs)
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{
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typedef struct { __vector128 _[__NUM_VXRS]; } addrtype;
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asm volatile(
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" la 1,%0\n"
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" .word 0xe70f,0x1000,0x003e\n" /* vstm 0,15,0(1) */
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" .word 0xe70f,0x1100,0x0c3e\n" /* vstm 16,31,256(1) */
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: "=Q" (*(addrtype *) vxrs) : : "1");
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}
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static inline void save_vx_regs_safe(__vector128 *vxrs)
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{
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unsigned long cr0, flags;
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flags = arch_local_irq_save();
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__ctl_store(cr0, 0, 0);
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__ctl_set_bit(0, 17);
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__ctl_set_bit(0, 18);
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save_vx_regs(vxrs);
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__ctl_load(cr0, 0, 0);
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arch_local_irq_restore(flags);
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}
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static inline void restore_vx_regs(__vector128 *vxrs)
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{
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typedef struct { __vector128 _[__NUM_VXRS]; } addrtype;
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asm volatile(
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" la 1,%0\n"
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" .word 0xe70f,0x1000,0x0036\n" /* vlm 0,15,0(1) */
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" .word 0xe70f,0x1100,0x0c36\n" /* vlm 16,31,256(1) */
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: : "Q" (*(addrtype *) vxrs) : "1");
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}
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static inline void save_fp_vx_regs(struct task_struct *task)
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{
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if (task->thread.vxrs)
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save_vx_regs(task->thread.vxrs);
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else
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save_fp_regs(task->thread.fp_regs.fprs);
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}
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static inline void restore_fp_vx_regs(struct task_struct *task)
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{
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if (task->thread.vxrs)
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restore_vx_regs(task->thread.vxrs);
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else
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restore_fp_regs(task->thread.fp_regs.fprs);
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}
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static inline void save_access_regs(unsigned int *acrs)
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{
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typedef struct { int _[NUM_ACRS]; } acrstype;
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asm volatile("stam 0,15,%0" : "=Q" (*(acrstype *)acrs));
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}
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static inline void restore_access_regs(unsigned int *acrs)
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{
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typedef struct { int _[NUM_ACRS]; } acrstype;
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asm volatile("lam 0,15,%0" : : "Q" (*(acrstype *)acrs));
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}
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#define switch_to(prev,next,last) do { \
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if (prev->mm) { \
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save_fp_ctl(&prev->thread.fp_regs.fpc); \
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save_fp_vx_regs(prev); \
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save_access_regs(&prev->thread.acrs[0]); \
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save_ri_cb(prev->thread.ri_cb); \
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} \
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if (next->mm) { \
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update_cr_regs(next); \
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restore_fp_ctl(&next->thread.fp_regs.fpc); \
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restore_fp_vx_regs(next); \
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restore_access_regs(&next->thread.acrs[0]); \
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restore_ri_cb(next->thread.ri_cb, prev->thread.ri_cb); \
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} \
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prev = __switch_to(prev,next); \
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} while (0)
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#endif /* __ASM_SWITCH_TO_H */
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