285f5fa7e9
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
65 lines
2.1 KiB
C
65 lines
2.1 KiB
C
#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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#include <asm/arch/hardware.h>
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/*
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* Physical DRAM offset.
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*/
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#define PHYS_OFFSET UL(0x00000000)
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#define TASK_SIZE UL(0x3f000000)
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#define PAGE_OFFSET UL(0x40000000)
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#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
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#ifndef __ASSEMBLY__
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#if defined(CONFIG_ARCH_IOP13XX)
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#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
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#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
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#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
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#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
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/*
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* Virtual view <-> PCI DMA view memory address translations
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* virt_to_bus: Used to translate the virtual address to an
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* address suitable to be passed to set_dma_addr
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* bus_to_virt: Used to convert an address for DMA operations
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* to an address that the kernel can use.
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*/
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/* RAM has 1:1 mapping on the PCIe/x Busses */
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#define __virt_to_bus(x) (__virt_to_phys(x))
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#define __bus_to_virt(x) (__phys_to_virt(x))
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#define virt_to_lbus(x) \
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(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \
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((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \
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((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
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((x) - PAGE_OFFSET + PHYS_OFFSET))
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#define lbus_to_virt(x) \
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(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
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((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
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((x) - PHYS_OFFSET + PAGE_OFFSET))
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/* Device is an lbus device if it is on the platform bus of the IOP13XX */
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#define is_lbus_device(dev) (dev &&\
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(strncmp(dev->bus->name, "platform", 8) == 0))
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#define __arch_page_to_dma(dev, page) \
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({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
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(dma_addr_t)__virt_to_bus(page_address(page));})
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#define __arch_dma_to_virt(dev, addr) \
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({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
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#define __arch_virt_to_dma(dev, addr) \
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({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
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#endif /* CONFIG_ARCH_IOP13XX */
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#endif /* !ASSEMBLY */
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#define PFN_TO_NID(addr) (0)
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#endif
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