![Alan Cox](/assets/img/avatar_default.png)
This is the grungy swap all the occurrences in the right places patch that goes with the updates. At this point we have the same functionality as before (except that sgttyb() returns speeds not zero) and are ready to begin turning new stuff on providing nobody reports lots of bugs If you are a tty driver author converting an out of tree driver the only impact should be termios->ktermios name changes for the speed/property setting functions from your upper layers. If you are implementing your own TCGETS function before then your driver was broken already and its about to get a whole lot more painful for you so please fix it 8) Also fill in c_ispeed/ospeed on init for most devices, although the current code will do this for you anyway but I'd like eventually to lose that extra paranoia [akpm@osdl.org: bluetooth fix] [mp3@de.ibm.com: sclp fix] [mp3@de.ibm.com: warning fix for tty3270] [hugh@veritas.com: fix tty_ioctl powerpc build] [jdike@addtoit.com: uml: fix ->set_termios declaration] Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Martin Peschke <mp3@de.ibm.com> Acked-by: Peter Oberparleiter <oberpar@de.ibm.com> Cc: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Jeff Dike <jdike@addtoit.com> Cc: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
824 lines
20 KiB
C
824 lines
20 KiB
C
/*
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* linux/drivers/char/amba.c
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*
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* Driver for AMBA serial ports
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* Copyright 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
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*
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* This is a generic driver for ARM AMBA-type serial ports. They
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* have a lot of 16550-like features, but are not register compatible.
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* Note that although they do have CTS, DCD and DSR inputs, they do
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* not have an RI input, nor do they have DTR or RTS outputs. If
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* required, these have to be supplied via some other means (eg, GPIO)
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* and hooked into this driver.
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*/
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#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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#define UART_NR 14
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#define SERIAL_AMBA_MAJOR 204
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#define SERIAL_AMBA_MINOR 64
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#define SERIAL_AMBA_NR UART_NR
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#define AMBA_ISR_PASS_LIMIT 256
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#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
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#define UART_DUMMY_DR_RX (1 << 16)
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/*
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* We wrap our port structure around the generic uart_port.
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*/
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struct uart_amba_port {
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struct uart_port port;
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struct clk *clk;
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unsigned int im; /* interrupt mask */
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unsigned int old_status;
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};
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static void pl011_stop_tx(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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uap->im &= ~UART011_TXIM;
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writew(uap->im, uap->port.membase + UART011_IMSC);
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}
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static void pl011_start_tx(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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uap->im |= UART011_TXIM;
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writew(uap->im, uap->port.membase + UART011_IMSC);
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}
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static void pl011_stop_rx(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
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UART011_PEIM|UART011_BEIM|UART011_OEIM);
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writew(uap->im, uap->port.membase + UART011_IMSC);
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}
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static void pl011_enable_ms(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
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writew(uap->im, uap->port.membase + UART011_IMSC);
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}
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static void pl011_rx_chars(struct uart_amba_port *uap)
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{
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struct tty_struct *tty = uap->port.info->tty;
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unsigned int status, ch, flag, max_count = 256;
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status = readw(uap->port.membase + UART01x_FR);
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while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
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ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
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flag = TTY_NORMAL;
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uap->port.icount.rx++;
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/*
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* Note that the error handling code is
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* out of the main execution path
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*/
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if (unlikely(ch & UART_DR_ERROR)) {
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if (ch & UART011_DR_BE) {
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ch &= ~(UART011_DR_FE | UART011_DR_PE);
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uap->port.icount.brk++;
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if (uart_handle_break(&uap->port))
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goto ignore_char;
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} else if (ch & UART011_DR_PE)
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uap->port.icount.parity++;
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else if (ch & UART011_DR_FE)
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uap->port.icount.frame++;
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if (ch & UART011_DR_OE)
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uap->port.icount.overrun++;
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ch &= uap->port.read_status_mask;
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if (ch & UART011_DR_BE)
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flag = TTY_BREAK;
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else if (ch & UART011_DR_PE)
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flag = TTY_PARITY;
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else if (ch & UART011_DR_FE)
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flag = TTY_FRAME;
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}
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if (uart_handle_sysrq_char(&uap->port, ch & 255))
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goto ignore_char;
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uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
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ignore_char:
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status = readw(uap->port.membase + UART01x_FR);
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}
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tty_flip_buffer_push(tty);
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return;
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}
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static void pl011_tx_chars(struct uart_amba_port *uap)
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{
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struct circ_buf *xmit = &uap->port.info->xmit;
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int count;
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if (uap->port.x_char) {
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writew(uap->port.x_char, uap->port.membase + UART01x_DR);
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uap->port.icount.tx++;
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uap->port.x_char = 0;
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return;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
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pl011_stop_tx(&uap->port);
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return;
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}
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count = uap->port.fifosize >> 1;
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do {
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writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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uap->port.icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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} while (--count > 0);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&uap->port);
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if (uart_circ_empty(xmit))
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pl011_stop_tx(&uap->port);
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}
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static void pl011_modem_status(struct uart_amba_port *uap)
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{
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unsigned int status, delta;
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status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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delta = status ^ uap->old_status;
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uap->old_status = status;
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if (!delta)
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return;
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if (delta & UART01x_FR_DCD)
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uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
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if (delta & UART01x_FR_DSR)
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uap->port.icount.dsr++;
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if (delta & UART01x_FR_CTS)
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uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
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wake_up_interruptible(&uap->port.info->delta_msr_wait);
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}
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static irqreturn_t pl011_int(int irq, void *dev_id)
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{
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struct uart_amba_port *uap = dev_id;
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unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
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int handled = 0;
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spin_lock(&uap->port.lock);
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status = readw(uap->port.membase + UART011_MIS);
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if (status) {
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do {
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writew(status & ~(UART011_TXIS|UART011_RTIS|
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UART011_RXIS),
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uap->port.membase + UART011_ICR);
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if (status & (UART011_RTIS|UART011_RXIS))
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pl011_rx_chars(uap);
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if (status & (UART011_DSRMIS|UART011_DCDMIS|
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UART011_CTSMIS|UART011_RIMIS))
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pl011_modem_status(uap);
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if (status & UART011_TXIS)
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pl011_tx_chars(uap);
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if (pass_counter-- == 0)
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break;
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status = readw(uap->port.membase + UART011_MIS);
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} while (status != 0);
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handled = 1;
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}
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spin_unlock(&uap->port.lock);
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return IRQ_RETVAL(handled);
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}
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static unsigned int pl01x_tx_empty(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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unsigned int status = readw(uap->port.membase + UART01x_FR);
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return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
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}
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static unsigned int pl01x_get_mctrl(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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unsigned int result = 0;
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unsigned int status = readw(uap->port.membase + UART01x_FR);
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#define BIT(uartbit, tiocmbit) \
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if (status & uartbit) \
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result |= tiocmbit
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BIT(UART01x_FR_DCD, TIOCM_CAR);
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BIT(UART01x_FR_DSR, TIOCM_DSR);
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BIT(UART01x_FR_CTS, TIOCM_CTS);
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BIT(UART011_FR_RI, TIOCM_RNG);
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#undef BIT
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return result;
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}
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static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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unsigned int cr;
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cr = readw(uap->port.membase + UART011_CR);
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#define BIT(tiocmbit, uartbit) \
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if (mctrl & tiocmbit) \
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cr |= uartbit; \
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else \
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cr &= ~uartbit
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BIT(TIOCM_RTS, UART011_CR_RTS);
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BIT(TIOCM_DTR, UART011_CR_DTR);
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BIT(TIOCM_OUT1, UART011_CR_OUT1);
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BIT(TIOCM_OUT2, UART011_CR_OUT2);
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BIT(TIOCM_LOOP, UART011_CR_LBE);
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#undef BIT
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writew(cr, uap->port.membase + UART011_CR);
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}
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static void pl011_break_ctl(struct uart_port *port, int break_state)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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unsigned long flags;
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unsigned int lcr_h;
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spin_lock_irqsave(&uap->port.lock, flags);
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lcr_h = readw(uap->port.membase + UART011_LCRH);
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if (break_state == -1)
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lcr_h |= UART01x_LCRH_BRK;
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else
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lcr_h &= ~UART01x_LCRH_BRK;
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writew(lcr_h, uap->port.membase + UART011_LCRH);
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spin_unlock_irqrestore(&uap->port.lock, flags);
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}
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static int pl011_startup(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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unsigned int cr;
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int retval;
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/*
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* Try to enable the clock producer.
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*/
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retval = clk_enable(uap->clk);
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if (retval)
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goto out;
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uap->port.uartclk = clk_get_rate(uap->clk);
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/*
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* Allocate the IRQ
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*/
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retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
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if (retval)
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goto clk_dis;
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writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
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uap->port.membase + UART011_IFLS);
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/*
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* Provoke TX FIFO interrupt into asserting.
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*/
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cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
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writew(cr, uap->port.membase + UART011_CR);
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writew(0, uap->port.membase + UART011_FBRD);
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writew(1, uap->port.membase + UART011_IBRD);
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writew(0, uap->port.membase + UART011_LCRH);
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writew(0, uap->port.membase + UART01x_DR);
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while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
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barrier();
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cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
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writew(cr, uap->port.membase + UART011_CR);
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/*
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* initialise the old status of the modem signals
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*/
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uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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/*
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* Finally, enable interrupts
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*/
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spin_lock_irq(&uap->port.lock);
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uap->im = UART011_RXIM | UART011_RTIM;
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writew(uap->im, uap->port.membase + UART011_IMSC);
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spin_unlock_irq(&uap->port.lock);
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return 0;
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clk_dis:
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clk_disable(uap->clk);
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out:
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return retval;
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}
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static void pl011_shutdown(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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unsigned long val;
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/*
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* disable all interrupts
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*/
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spin_lock_irq(&uap->port.lock);
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uap->im = 0;
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writew(uap->im, uap->port.membase + UART011_IMSC);
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writew(0xffff, uap->port.membase + UART011_ICR);
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spin_unlock_irq(&uap->port.lock);
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/*
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* Free the interrupt
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*/
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free_irq(uap->port.irq, uap);
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/*
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* disable the port
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*/
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writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
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/*
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* disable break condition and fifos
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*/
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val = readw(uap->port.membase + UART011_LCRH);
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val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
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writew(val, uap->port.membase + UART011_LCRH);
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/*
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* Shut down the clock producer
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*/
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clk_disable(uap->clk);
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}
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static void
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pl011_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int lcr_h, old_cr;
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unsigned long flags;
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unsigned int baud, quot;
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/*
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* Ask the core to calculate the divisor for us.
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*/
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baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
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quot = port->uartclk * 4 / baud;
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switch (termios->c_cflag & CSIZE) {
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case CS5:
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lcr_h = UART01x_LCRH_WLEN_5;
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break;
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case CS6:
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lcr_h = UART01x_LCRH_WLEN_6;
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break;
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case CS7:
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lcr_h = UART01x_LCRH_WLEN_7;
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break;
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default: // CS8
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lcr_h = UART01x_LCRH_WLEN_8;
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break;
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}
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if (termios->c_cflag & CSTOPB)
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lcr_h |= UART01x_LCRH_STP2;
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if (termios->c_cflag & PARENB) {
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lcr_h |= UART01x_LCRH_PEN;
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if (!(termios->c_cflag & PARODD))
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lcr_h |= UART01x_LCRH_EPS;
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}
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if (port->fifosize > 1)
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lcr_h |= UART01x_LCRH_FEN;
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spin_lock_irqsave(&port->lock, flags);
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/*
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* Update the per-port timeout.
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*/
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
|
|
port->read_status_mask = UART011_DR_OE | 255;
|
|
if (termios->c_iflag & INPCK)
|
|
port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
|
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
port->read_status_mask |= UART011_DR_BE;
|
|
|
|
/*
|
|
* Characters to ignore
|
|
*/
|
|
port->ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
|
|
if (termios->c_iflag & IGNBRK) {
|
|
port->ignore_status_mask |= UART011_DR_BE;
|
|
/*
|
|
* If we're ignoring parity and break indicators,
|
|
* ignore overruns too (for real raw support).
|
|
*/
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |= UART011_DR_OE;
|
|
}
|
|
|
|
/*
|
|
* Ignore all characters if CREAD is not set.
|
|
*/
|
|
if ((termios->c_cflag & CREAD) == 0)
|
|
port->ignore_status_mask |= UART_DUMMY_DR_RX;
|
|
|
|
if (UART_ENABLE_MS(port, termios->c_cflag))
|
|
pl011_enable_ms(port);
|
|
|
|
/* first, disable everything */
|
|
old_cr = readw(port->membase + UART011_CR);
|
|
writew(0, port->membase + UART011_CR);
|
|
|
|
/* Set baud rate */
|
|
writew(quot & 0x3f, port->membase + UART011_FBRD);
|
|
writew(quot >> 6, port->membase + UART011_IBRD);
|
|
|
|
/*
|
|
* ----------v----------v----------v----------v-----
|
|
* NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
|
|
* ----------^----------^----------^----------^-----
|
|
*/
|
|
writew(lcr_h, port->membase + UART011_LCRH);
|
|
writew(old_cr, port->membase + UART011_CR);
|
|
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
static const char *pl011_type(struct uart_port *port)
|
|
{
|
|
return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
|
|
}
|
|
|
|
/*
|
|
* Release the memory region(s) being used by 'port'
|
|
*/
|
|
static void pl010_release_port(struct uart_port *port)
|
|
{
|
|
release_mem_region(port->mapbase, SZ_4K);
|
|
}
|
|
|
|
/*
|
|
* Request the memory region(s) being used by 'port'
|
|
*/
|
|
static int pl010_request_port(struct uart_port *port)
|
|
{
|
|
return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
|
|
!= NULL ? 0 : -EBUSY;
|
|
}
|
|
|
|
/*
|
|
* Configure/autoconfigure the port.
|
|
*/
|
|
static void pl010_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE) {
|
|
port->type = PORT_AMBA;
|
|
pl010_request_port(port);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* verify the new serial_struct (for TIOCSSERIAL).
|
|
*/
|
|
static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
{
|
|
int ret = 0;
|
|
if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
|
|
ret = -EINVAL;
|
|
if (ser->irq < 0 || ser->irq >= NR_IRQS)
|
|
ret = -EINVAL;
|
|
if (ser->baud_base < 9600)
|
|
ret = -EINVAL;
|
|
return ret;
|
|
}
|
|
|
|
static struct uart_ops amba_pl011_pops = {
|
|
.tx_empty = pl01x_tx_empty,
|
|
.set_mctrl = pl011_set_mctrl,
|
|
.get_mctrl = pl01x_get_mctrl,
|
|
.stop_tx = pl011_stop_tx,
|
|
.start_tx = pl011_start_tx,
|
|
.stop_rx = pl011_stop_rx,
|
|
.enable_ms = pl011_enable_ms,
|
|
.break_ctl = pl011_break_ctl,
|
|
.startup = pl011_startup,
|
|
.shutdown = pl011_shutdown,
|
|
.set_termios = pl011_set_termios,
|
|
.type = pl011_type,
|
|
.release_port = pl010_release_port,
|
|
.request_port = pl010_request_port,
|
|
.config_port = pl010_config_port,
|
|
.verify_port = pl010_verify_port,
|
|
};
|
|
|
|
static struct uart_amba_port *amba_ports[UART_NR];
|
|
|
|
#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
|
|
|
|
static void pl011_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
|
|
|
while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
|
|
barrier();
|
|
writew(ch, uap->port.membase + UART01x_DR);
|
|
}
|
|
|
|
static void
|
|
pl011_console_write(struct console *co, const char *s, unsigned int count)
|
|
{
|
|
struct uart_amba_port *uap = amba_ports[co->index];
|
|
unsigned int status, old_cr, new_cr;
|
|
|
|
clk_enable(uap->clk);
|
|
|
|
/*
|
|
* First save the CR then disable the interrupts
|
|
*/
|
|
old_cr = readw(uap->port.membase + UART011_CR);
|
|
new_cr = old_cr & ~UART011_CR_CTSEN;
|
|
new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
|
|
writew(new_cr, uap->port.membase + UART011_CR);
|
|
|
|
uart_console_write(&uap->port, s, count, pl011_console_putchar);
|
|
|
|
/*
|
|
* Finally, wait for transmitter to become empty
|
|
* and restore the TCR
|
|
*/
|
|
do {
|
|
status = readw(uap->port.membase + UART01x_FR);
|
|
} while (status & UART01x_FR_BUSY);
|
|
writew(old_cr, uap->port.membase + UART011_CR);
|
|
|
|
clk_disable(uap->clk);
|
|
}
|
|
|
|
static void __init
|
|
pl011_console_get_options(struct uart_amba_port *uap, int *baud,
|
|
int *parity, int *bits)
|
|
{
|
|
if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
|
|
unsigned int lcr_h, ibrd, fbrd;
|
|
|
|
lcr_h = readw(uap->port.membase + UART011_LCRH);
|
|
|
|
*parity = 'n';
|
|
if (lcr_h & UART01x_LCRH_PEN) {
|
|
if (lcr_h & UART01x_LCRH_EPS)
|
|
*parity = 'e';
|
|
else
|
|
*parity = 'o';
|
|
}
|
|
|
|
if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
|
|
*bits = 7;
|
|
else
|
|
*bits = 8;
|
|
|
|
ibrd = readw(uap->port.membase + UART011_IBRD);
|
|
fbrd = readw(uap->port.membase + UART011_FBRD);
|
|
|
|
*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
|
|
}
|
|
}
|
|
|
|
static int __init pl011_console_setup(struct console *co, char *options)
|
|
{
|
|
struct uart_amba_port *uap;
|
|
int baud = 38400;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
/*
|
|
* Check whether an invalid uart number has been specified, and
|
|
* if so, search for the first available port that does have
|
|
* console support.
|
|
*/
|
|
if (co->index >= UART_NR)
|
|
co->index = 0;
|
|
uap = amba_ports[co->index];
|
|
|
|
uap->port.uartclk = clk_get_rate(uap->clk);
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
else
|
|
pl011_console_get_options(uap, &baud, &parity, &bits);
|
|
|
|
return uart_set_options(&uap->port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver amba_reg;
|
|
static struct console amba_console = {
|
|
.name = "ttyAMA",
|
|
.write = pl011_console_write,
|
|
.device = uart_console_device,
|
|
.setup = pl011_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &amba_reg,
|
|
};
|
|
|
|
#define AMBA_CONSOLE (&amba_console)
|
|
#else
|
|
#define AMBA_CONSOLE NULL
|
|
#endif
|
|
|
|
static struct uart_driver amba_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "ttyAMA",
|
|
.dev_name = "ttyAMA",
|
|
.major = SERIAL_AMBA_MAJOR,
|
|
.minor = SERIAL_AMBA_MINOR,
|
|
.nr = UART_NR,
|
|
.cons = AMBA_CONSOLE,
|
|
};
|
|
|
|
static int pl011_probe(struct amba_device *dev, void *id)
|
|
{
|
|
struct uart_amba_port *uap;
|
|
void __iomem *base;
|
|
int i, ret;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
|
|
if (amba_ports[i] == NULL)
|
|
break;
|
|
|
|
if (i == ARRAY_SIZE(amba_ports)) {
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
uap = kmalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
|
|
if (uap == NULL) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
base = ioremap(dev->res.start, PAGE_SIZE);
|
|
if (!base) {
|
|
ret = -ENOMEM;
|
|
goto free;
|
|
}
|
|
|
|
memset(uap, 0, sizeof(struct uart_amba_port));
|
|
uap->clk = clk_get(&dev->dev, "UARTCLK");
|
|
if (IS_ERR(uap->clk)) {
|
|
ret = PTR_ERR(uap->clk);
|
|
goto unmap;
|
|
}
|
|
|
|
uap->port.dev = &dev->dev;
|
|
uap->port.mapbase = dev->res.start;
|
|
uap->port.membase = base;
|
|
uap->port.iotype = UPIO_MEM;
|
|
uap->port.irq = dev->irq[0];
|
|
uap->port.fifosize = 16;
|
|
uap->port.ops = &amba_pl011_pops;
|
|
uap->port.flags = UPF_BOOT_AUTOCONF;
|
|
uap->port.line = i;
|
|
|
|
amba_ports[i] = uap;
|
|
|
|
amba_set_drvdata(dev, uap);
|
|
ret = uart_add_one_port(&amba_reg, &uap->port);
|
|
if (ret) {
|
|
amba_set_drvdata(dev, NULL);
|
|
amba_ports[i] = NULL;
|
|
clk_put(uap->clk);
|
|
unmap:
|
|
iounmap(base);
|
|
free:
|
|
kfree(uap);
|
|
}
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int pl011_remove(struct amba_device *dev)
|
|
{
|
|
struct uart_amba_port *uap = amba_get_drvdata(dev);
|
|
int i;
|
|
|
|
amba_set_drvdata(dev, NULL);
|
|
|
|
uart_remove_one_port(&amba_reg, &uap->port);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
|
|
if (amba_ports[i] == uap)
|
|
amba_ports[i] = NULL;
|
|
|
|
iounmap(uap->port.membase);
|
|
clk_put(uap->clk);
|
|
kfree(uap);
|
|
return 0;
|
|
}
|
|
|
|
static struct amba_id pl011_ids[] __initdata = {
|
|
{
|
|
.id = 0x00041011,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{ 0, 0 },
|
|
};
|
|
|
|
static struct amba_driver pl011_driver = {
|
|
.drv = {
|
|
.name = "uart-pl011",
|
|
},
|
|
.id_table = pl011_ids,
|
|
.probe = pl011_probe,
|
|
.remove = pl011_remove,
|
|
};
|
|
|
|
static int __init pl011_init(void)
|
|
{
|
|
int ret;
|
|
printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
|
|
|
|
ret = uart_register_driver(&amba_reg);
|
|
if (ret == 0) {
|
|
ret = amba_driver_register(&pl011_driver);
|
|
if (ret)
|
|
uart_unregister_driver(&amba_reg);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void __exit pl011_exit(void)
|
|
{
|
|
amba_driver_unregister(&pl011_driver);
|
|
uart_unregister_driver(&amba_reg);
|
|
}
|
|
|
|
module_init(pl011_init);
|
|
module_exit(pl011_exit);
|
|
|
|
MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
|
|
MODULE_DESCRIPTION("ARM AMBA serial port driver");
|
|
MODULE_LICENSE("GPL");
|